数字逻辑课程设计电子钟
2017-08-16 17:58
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(1) 模8计数器
library ieee;
use ieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entity mo8 is
port(
clk,clr:in std_logic;
ql:out std_logic_vector(2 downto 0);
co:out std_logic);
end mo8;
architecture rtl of mo8 is
signal qcl :std_logic_vector(2 downto 0);
begin
process(clk)
begin
if(clr='0') then
qcl<="000";
elsif(clk'event and clk='1') then
if(qcl="111") then
qcl<="000";co<='1';
else
qcl<=qcl+'1';co<='0';
end if;
end if;
ql<=qcl;
end process;
end rtl;
(2) 模24计数器
library ieee;
use ieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entity mo24 is
port(
clk,clr:in std_logic;
en:in std_logic;
ql,qh:out std_logic_vector(3 downto 0);
co:out std_logic);
end mo24;
architecture rtl of mo24 is
signal qcl:std_logic_vector(3 downto 0);
signal qch:std_logic_vector(3 downto 0);
begin
process(clk)
begin
if(clr='0')then
qcl<="0000";qch<="0000";
elsif(clk'event and clk='1')then
co<='0';
if(en='1' and qch="0010"andqcl="0011")then
qcl<="0000";qch<="0000";co<='1';
else
if(en='1' andqcl<"1001")then
qcl<=qcl+'1';
elsif(en='1' andqcl="1001")then
qch<=qch+'1';qcl<="0000";
end if;
end if;
end if;
qh<=qch;ql<=qcl;
end process;
end rtl;
(3) 模60计数器
library ieee;
use ieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entity mo60 is
port(
clk,clr:in std_logic;
en:in std_logic;
ql,qh:out std_logic_vector(3 downto 0);
co:out std_logic);
end mo60;
architecture rtl of mo60 is
signal qcl:std_logic_vector(3 downto 0);
signal qch:std_logic_vector(3 downto 0);
begin
process(clk)
begin
if(clr='0')then
qcl<="0000";qch<="0000";
elsif(clk'event and clk='1')then
co<='0';
if(en='1' and qch="0101"andqcl="1001")then
qcl<="0000";qch<="0000";co<='1';
else
if(en='1' andqcl<"1001")then
qcl<=qcl+'1';
elsif(en='1' andqcl="1001")then
qch<=qch+'1';qcl<="0000";
end if;
end if;
end if;
qh<=qch;ql<=qcl;
end process;
end rtl;
(4) 分频器
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
useieee.std_logic_unsigned.all;
entity fenpin is
port(
clk:in std_logic;
clk1024,clk512,clk4,clk1:out std_logic);
end fenpin;
architecture rtl of fenpin is
signal ql:std_logic_vector(9downto 0);
begin
process(clk)
begin
if(clk'event and clk='1')then
if(ql="1111111111")then
ql<="0000000000";
else
ql<=ql+1;
end if;
end if;
end process;
clk1024<=clk;
clk512<=ql(0);
clk4<=ql(8);
clk1<=ql(9);
end rtl;
(5) 闹钟
library ieee;
use ieee.std_logic_1164.all;
entity naozhong is
port(
cp1,cp512,cp1024,en:in std_logic;
hourh,hourl,sethourh,sethourl:in std_logic_vector(3 downto 0);
minh,minl,setminh,setminl:in std_logic_vector(3 downto 0);
sech,secl:in std_logic_vector(3 downto 0);
r:out std_logic);
end naozhong;
architecture rtl of naozhongis
begin
process(en,hourh,hourl,sethourh,sethourl,minh,minl,setminh,setminl,cp1,cp512,cp1024)
begin
if(en='1')then
if(hourh=sethourh and hourl=sethourl andminh=setminh and minl=setminl)then
if(cp1='1')then
r<=cp512;
else
r<=cp1024;
end if;
end if;
end if;
end process;
end rtl;
(6) 整点报时
library ieee;
use ieee.std_logic_1164.all;
entity baoshi is
port(
cp1,cp512,cp1024,en:in std_logic;
hourh,hourl,minh,minl,sech,secl:in std_logic_vector(3 downto 0);
r:out std_logic);
end baoshi;
architecture rtl of baoshi is
begin
process(cp1,cp512,cp1024,en,hourh,hourl,minh,minl,sech,secl)
begin
if(en='1')then
if(minh="0101" andminl="1001" and sech="0101")then
if(secl="0001" orsecl="0011" or secl="0101" or secl="0111")then
r<=cp512;
elsif(secl="1001")then
r<=cp1024;
else
r<='0';
end if;
end if;
end if;
end process;
end rtl;
(7) 定闹钟
Hour：
library ieee;
use ieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entity hour is
port(
clk:in std_logic;
set:in std_logic;
ql,qh:out std_logic_vector(3 downto 0));
end hour;
architecture rtl of hour is
signal qcl:std_logic_vector(3downto 0);
signal qch:std_logic_vector(3downto 0);
begin
process(clk)
begin
if(set='1')then
if(clk'event and clk='1')then
if(qch="0101" andqcl="1001")then
qch<="0000";qcl<="0000";
else
if(qcl="1001")then
qch<=qch+'1';qcl<="0000";
elsif(qcl<"1001")then
qcl<=qcl+'1';
end if;
end if;
end if;
end if;
qh<=qch;ql<=qcl;
end process;
end rtl;
Minutes：
library ieee;
use ieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entity minute is
port(
clk:in std_logic;
set:in std_logic;
ql,qh:out std_logic_vector(3 downto 0));
end minute;
architecture rtl of minute is
signal qcl:std_logic_vector(3downto 0);
signal qch:std_logic_vector(3downto 0);
begin
process(clk)
begin
if(set='1')then
if(clk'event and clk='1')then
if(qch="0101" andqcl="1001")then
qch<="0000";qcl<="0000";
else
if(qcl="1001")then
qch<=qch+'1';qcl<="0000";
elsif(qcl<"1001")then
qcl<=qcl+'1';
end if;
end if;
end if;
end if;
ql<=qcl;qh<=qch;
end process;
end rtl;
(8) 二选一
A：
library ieee;
use ieee.std_logic_1164.all;
entity xuanze2 is
port(
a,b:in std_logic;
set:in std_logic;
y: out std_logic);
end xuanze2;
architecture rtl of xuanze2 is
begin
process(a,b,set)
begin
if(set='1')then
y<=a;
else
y<=b;
end if;
end process;
end rtl;
B：
library ieee;
use ieee.std_logic_1164.all;
entity xuanze is
port(
y1:in std_logic_vector(3 downto 0);
y2:in std_logic_vector(3 downto 0);
set:in std_logic;
d:out std_logic_vector(3 downto 0));
end xuanze;
architecture rtl of xuanze is
begin
process(y1,y2,set)
begin
if(set='1')then
d<=y1;
else
d<=y2;
end if;
end process;
end rtl;
(9) 七段译码器
library ieee;
use ieee.std_logic_1164.all;
entity duan7 is
port(
d :in std_logic_vector(3 downto 0);
p:out std_logic_vector(6 downto 0));
end duan7;
architecture rtl of duan7 is
begin
process(d)
begin
case d is
when"0000"=>p<="1111110";
when"0001"=>p<="0110000";
when"0010"=>p<="1101101";
when"0011"=>p<="1111001";
when "0100"=>p<="0110011";
when"0101"=>p<="1011011";
when"0110"=>p<="1011111";
when"0111"=>p<="1110000";
when"1000"=>p<="1111111";
when"1001"=>p<="1111011";
when others =>p<="0000001";
end case;
end process;
end rtl;
(10) 八选一选择器
library ieee;
use ieee.std_logic_1164.all;
entity choice8 is
port(
d0,d1,d2,d3,d4,d5,d6,d7:in std_logic_vector(3 downto 0);
sel:in std_logic_vector(2 downto 0);
y:out std_logic_vector(3 downto 0));
end choice8;
architecture rtl of choice8 is
begin
process(sel)
begin
case sel is
when "000"=>y<=d0;
when "001"=>y<=d1;
when "010"=>y<=d2;
when "011"=>y<=d3;
when "100"=>y<=d4;
when "101"=>y<=d5;
when "110"=>y<=d6;
when "111"=>y<=d7;
when others =>y<="0000";
end case;
end process;
end rtl;
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