MIPI转换芯片 转接IC ZA7783A：MIPI DSI转RGB/LVDS芯片

1 Overview

       ZA7783 is a bridge chip which supports three kinds of display interfaces:

 MIPI DSI RX Interface (1 Clock Lane + 4 Data Lanes)

 LVDS TX Interface (1 Clock Lane + 4 Data Lanes)

 MIPI DPI TX/RX Interface (PCLK + RGB888 + VSYNC + HSYNC +DATAEN)

   The chip bridges these display interfaces in three working modes:

 MODE1: MIPI DSI RX => LVDS TX

 MODE2: MIPI DSI RX => DPI TX

 MODE3: DPI RX => LVDS TX

       Besides, there is also an I2C control interface (XCLK + I2C_SCL + I2C_SDA) for the host chip (AP or BB) to access ZA7783’s software registers.Analog IPs of ZA7783 are supplied by 3.3V voltage (typical). For Digital IOs, the host interface (XCLK + I2C_SCL
+ I2C_SDA) is supplied by DVDD18 (PIN32),while the DPI interface (PCLK + RGB888 + VSYNC + HSYNC + DATAEN) is supplied by DVDD33 (PIN45 and PIN59). Thus, ZA7783 is able to bridge AP or BB with 1.8V IO to RGB Panel with 3.3V IO. Besides, an embedded LDO converts
3.3V to 1.2V to supply the chip’s internal digital logic. In addition, an embedded POR implements a power on reset to the whole chip.
2 Target Applications

       Tablet PC
3 Feature Description

       MIPI DSI RX Interface

 Compliant to MIPI DSI V1.01 and MIPI D-PHY V1.00

 1 Clock Lane + 4 Data Lanes

 Data rate up to 600Mbps per data lane (300MHz high-speed clock on clock lane)

 2.4Gbps bandwidth on four data lanes in total, giving a display resolution up to 1366x768 24bpp @ 60fps

 Only support MIPI DSI Video Mode (Non-Burst Mode with Sync Pulses) and all lanes are unidirectional from the host chip to the bridge chip

 The host chip is required to provide continuous high-speed clock

 Only support using all of the four data lanes, in other words, using part of them is not supported

 Support multiple packets within a single high-speed transmission

 Ignore received virtual channel field

 Only the following packet data types are supported:

6'h01=Sync Event, V Sync Start (Short)

6'h11=Sync Event, V Sync End (Short)

6'h21=Sync Event, H Sync Start (Short)

6'h31=Sync Event, H Sync End (Short)

6'h08=End of Transimission packet (EoTp) (Short)

6'h09=Null Packet, no data (Long)

6'h19=Blanking Packet, no data (Long)

6'h2E=Loosely Packed Pixel Stream, 18-bit RGB, 6-6-6 Format (Long)

6'h3E=Packed Pixel Stream, 24-bit RGB, 8-8-8 Format (Long)

        The other packet data types cannot be handled and must not be sent to ZA7783!

 Ignore received ecc field

 Ignore received checksum field

 RGB565 Packed Pixel Stream and RGB666 Packed Pixel Stream are not supported

 For a data lane, the connection of Dp/Dn can be exchanged

 The order of the four data lanes can be configured

 Dither function for converting RGB888 to RGB666
LVDS TX Interface

 Compliant to LVDS Spec

 1 Clock Lane + 4 Data Lanes

 Support RGB888 and RGB666

RGB888: 1 Clock Lane + 4 Data Lanes

RGB666: 1 Clock Lane + 3 Data Lanes

 Support NS Mode and JEIDA Mode

 The polarity of VSYNC/HSYNC/DATAEN can be configured

 For a data lane, the connection of Dp/Dn can be exchanged

 The order of the four data lanes can be configured

 Dither function for converting RGB888 to RGB666
DPI TX/RX Interface

 PCLK + RGB888 + VSYNC + HSYNC + DATAEN

 The edge of PCLK can be configured

 The polarity of VSYNC/HSYNC/DATAEN can be configured
I2C Interface

 An external clock XCLK should be provided (e.g. 26MHz)

 Up to 400Kbps
 I2C Slave ID is 0x37

4 Functional Block Diagram

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5 Pin Configuration


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