转接IC ICN6202：MIPI DSI转LVDS芯片

1 Introduction

    ICN6201 is a bridge chip which receives MIPI® DSI inputs and sends LVDS outputs.

    MIPI® DSI supports up to 4 lanes and each lane operates at 1Gbps maximum; the totally maximum input bandwidth is 4Gbps; and the MIPI defined ULPS(ultra-low-power state) is also supported. ICN6201 decodes MIPI® DSI 18bepp RGB666 and 24bpp RGB888 packets.

    The LVDS output 18 or 24 bits pixel with 25MHz to 154MHz, by VESA or JEIDA format.

    ICN6201 support video resolution up to FHD (1920x1080) and WUXGA(1920x1200).

    ICN6201 adopts QFN40 and QFN 48pins package.

1.1 Feature List

     Supports MIPI® D-PHY Version 1.00.00 and MIPI® DSI Version 1.02.00.

     Single Channel DSI Receiver with One, Two, Three and Four lanes configurable, each lanes operates up to 1Gbps.

     Receives 18bpp RGB666 and 24bpp RGB888 packets defined by DSI.

     Supports MIPI Low State, Ultra-Low Power State, Shut Down mode.

     Single Channel LVDS with output clock range of 25MHz to 154MHz.

     LVDS can be generated from MIPI HS clock or external reference clock.

     Support LVDS clock with center spreading up to 2%, modulation 30KHz ~ 60KHz.

     LVDS output with VESA or JEIDA format.

     LVDS output pin order can be swapped flexible.

     supply voltage: 1.8V.

     provide I2C slave interface.

     package: QFN40-pins with e-pad.
     Package: QFN48-pins with e-pad.

2 Functional Block Diagram

Following figure shows a functional block diagram of the ICN6201.



3 System Application Diagram

In the diagram below shows the ICN6201’s system application.


4 Pin Diagram

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