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Modelsim do脚本文件简单范例

2016-06-25 22:05 260 查看

vlog -work Top_work F_V_tb.v F_S.v

vlib Top_work

vmap work Top_work

vlog FIFO.v FSMC.v TOP_Design.v TOP_Designtb.v

vsim -gui -novopt Top_work.TOP_Design_vlg_tst

add wave -r /*

add wave sim:/TOP_Design_vlg_tst/*

add wave -position end /TOP_Design_vlg_tst/i1/FIFO_Master/rd

add wave -position insertpoint /TOP_Design_vlg_tst/i1/FIFO_Master/wr

add wave -position insertpoint /TOP_Design_vlg_tst/i1/FIFO_Master/fifo_in

add wave -position insertpoint /TOP_Design_vlg_tst/i1/FIFO_Master/fifo_out

add wave -position insertpoint /TOP_Design_vlg_tst/i1/FIFO_Master/fifo_full

add wave -position insertpoint /TOP_Design_vlg_tst/i1/FIFO_Master/fifo_empty

add wave -position insertpoint /TOP_Design_vlg_tst/i1/FIFO_Master/counter

add wave -position insertpoint /TOP_Design_vlg_tst/i1/FIFO_Master/write_ptr

add wave -position insertpoint /TOP_Design_vlg_tst/i1/FIFO_Master/read_ptr

add wave -position insertpoint /TOP_Design_vlg_tst/i1/Fsmc/current_state

add wave -position insertpoint /TOP_Design_vlg_tst/i1/Fsmc/next_state

run -all
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标签:  Verilog