【原创】The solutional manual of the Verilog HDL: A Guide to Digital Design and Synthesis (2nd)—ch07-II

7. Design a negative edge-triggered D-flipflop(D_FF) with synchronous clear, active high (D_FF clears only at a negative edge of clock when clear is high). Use behavioral statements only. (Hint: Output q of D_FF must be declared as reg). Design a clock with a period of 10 units and test the D_FF.

my answer:













8. Design the D-flipflop in exercise 7 with asynchronous clear (D_FF clears whenever clear goes high. It does not wait for next negative edge). Test the D_FF.

my answer:









9. Using the wait statement, design a level-sensitive latch that takes clock and d as inputs and q as output. q=d whenever clock=1.

my answer:













(p.s. 在modelsim 6.5b里测试，if可以仿真，wait会卡死。L).

10. Design the 4-to-1 multiplexer in eg 7-19 by using if and else statements. The port interface must remain the same.

my answer:













11. Design the traffic signal controller discussed in this chapter by using if and else statements.

my answer:

`define TRUE 1'b1;

`define FALSE 1'b0;

//Delays

`define Y2RDELAY 3 //Yellow to red delay

`define R2GDELAY 2 //Red to green delay

module sig_control

(hwy,cntry,X,clock,clear);

//I/O ports

output [1:0] hwy, cntry;

//2-bit output for 3 states of signal

//GREEN, YELLOW, RED

reg [1:0] hwy,cntry;

//declared output signals are registers

input X;

//if TRUE, indicates that there is car on

//the country road, otherwise FALSE

input clock,clear;

parameter RED=2'd0,

YELLOW=2'd1,

GREEN=2'd2;

//State definition HWY CONTRY

parameter S0=3'd0, //GREEN RED

S1=3'd1, //YELLOW RED

S2=3'd2, //RED RED

S3=3'd3, //RED GREEN

S4=3'd4; //RED YELLOW

//Internal state variables

reg [2:0] state;

reg [2:0] next_state;

//state changes only at postive edge of clock

always @(posedge clock)

if(clear)

state<=S0; //Controller starts in S0 state

else

state<=next_state; //State change

//Compute values of main signal and country signal

always @(state)

begin

//case(state)

//S0: ; //No change, use default

if(state==S1)

hwy=YELLOW;

else if(state==S2)

hwy=RED;

else if(state==S3)

begin

hwy=RED;

cntry=GREEN;

end

else if(state==S4)

begin

hwy=RED;

cntry=YELLOW;

end

else

begin

hwy=GREEN; //Default Light Assignment for Highway light

cntry=RED; //Default light Assignment for Country light

end

end

//State machine using case statements

always @(state or X)

begin

if(state==S0)

if(X)

next_state=S1;

else

next_state=S0;

else if(state== S1)

begin //delay some positive edges of clock

repeat(`Y2RDELAY) @(posedge clock);

next_state=S2;

end

else if(state== S2)

begin //delay some positive edges of clock

repeat(`R2GDELAY) @(posedge clock);

next_state=S3;

end

else if(state== S3)

if(X)

next_state=S3;

else

next_state=S4;

else

begin //delay some positive edges of clock

repeat(`Y2RDELAY) @(posedge clock);

next_state=S0;

end

//default:next_state=S0;

//endcase

end

endmodule