【原创】The solutional manual of the Verilog HDL: A Guide to Digital Design and Synthesis (2nd)--ch05

Chapter 5. Gate-level Modeling

5.4 Exercises

1. Create your own 2-input Verilog gates called my_or, my_and and my_not from 2-input nand gates. Check the functionality of these gates with a stimulus module.

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2. A 2-input xor gate can be built from my_and, my_or and my_not gates. Construct an xor module in Verilog that realizes the logic function, z=xy’+x’y. Inputs are x and y, and z is the output. Write a stimulus module that exercises all four combinations of x and y inputs.

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3. The 1-bit full adder described in the chapter can be expressed in a sum of products form.

sum=a.b.c_in+a’.b.c_in’+a’.b’.c_in+a.b’c_in’

c_out=a.b+b.c_in+a.c_in

Assuming a,b,c_in are the inputs and sum and c_out are the outputs, design a logic circuit to implement the 1-bit full adder, using only and, not ,and or gates. Write the Verilog description for the circuit. You may use up to 4-input Verilog primitive and and or gates. Write the stimulus for the full adder and check the functionality for all input combinations.

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4. The logic diagram for an RS latch with delay is shown below.





Write the Verilog description for the RS latch. Include delays of 1 unit when instantiating the nor gates. Write the stimulus module for the RS latch, using the following table, and verify the outputs.





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5. Design a 2-to-1 multiplexer using bufif0 and bufif1 gates as shown below.





The delay specification for gates b1 and b2 are as follows:

	Min	Typ	Max
Rise	1	2	3
Fall	3	4	5
Turnoff	5	6	7

Apply stimuls and test the output values.

my answer:

Reference

Smair Palnitkar, <Verilog HDL: A Guide to Digital Design and Synthesis (2nd) >