FPGA实验六——计数器、ROM和DDS
2017-12-03 22:08
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计数器、ROM和DDS
实验要求1：
用计数器生成地址、读取ROM数据用SignalTap观察ROM的输出波形
理解二进制补码和无符号数
修改技术增量值，观察波形变化，实考输出频率和计数器增量值的关系
①Verilog HDL代码
带增量输入的计数器模块
module cnt_incr( CLK , // clock INCR , // counter increase value CNTVAL); // counter value input CLK; input [7-1:0] INCR; output [7-1:0] CNTVAL; reg [7-1:0] CNTVAL; always @ (posedge CLK) begin CNTVAL <= INCR + CNTVAL; end endmodule // module cnt_incr
ROM代码
module sine_rom( CLK , // clock RA , // read address RD ); // read data input CLK; input [6 :0] RA; output [7 :0] RD; reg [7 :0] RD; always @ (posedge CLK) case(RA) 7 'd 0 :RD = #1 8 'b 00000000; // 0 0x0 7 'd 1 :RD = #1 8 'b 00000110; // 6 0x6 7 'd 2 :RD = #1 8 'b 00001100; // 12 0xC 7 'd 3 :RD = #1 8 'b 00010010; // 18 0x12 7 'd 4 :RD = #1 8 'b 00011000; // 24 0x18 7 'd 5 :RD = #1 8 'b 00011110; // 30 0x1E 7 'd 6 :RD = #1 8 'b 00100100; // 36 0x24 7 'd 7 :RD = #1 8 'b 00101010; // 42 0x2A 7 'd 8 :RD = #1 8 'b 00110000; // 48 0x30 7 'd 9 :RD = #1 8 'b 00110110; // 54 0x36 7 'd 10 :RD = #1 8 'b 00111011; // 59 0x3B 7 'd 11 :RD = #1 8 'b 01000001; // 65 0x41 7 'd 12 :RD = #1 8 'b 01000110; // 70 0x46 7 'd 13 :RD = #1 8 'b 01001011; // 75 0x4B 7 'd 14 :RD = #1 8 'b 01010000; // 80 0x50 7 'd 15 :RD = #1 8 'b 01010101; // 85 0x55 7 'd 16 :RD = #1 8 'b 01011001; // 89 0x59 7 'd 17 :RD = #1 8 'b 01011110; // 94 0x5E 7 'd 18 :RD = #1 8 'b 01100010; // 98 0x62 7 'd 19 :RD = #1 8 'b 01100110; // 102 0x66 7 'd 20 :RD = #1 8 'b 01101001; // 105 0x69 7 'd 21 :RD = #1 8 'b 01101100; // 108 0x6C 7 'd 22 :RD = #1 8 'b 01110000; // 112 0x70 7 'd 23 :RD = #1 8 'b 01110010; // 114 0x72 7 'd 24 :RD = #1 8 'b 01110101; // 117 0x75 7 'd 25 :RD = #1 8 'b 01110111; // 119 0x77 7 'd 26 :RD = #1 8 'b 01111001; // 121 0x79 7 'd 27 :RD = #1 8 'b 01111011; // 123 0x7B 7 'd 28 :RD = #1 8 'b 01111100; // 124 0x7C 7 'd 29 :RD = #1 8 'b 01111101; // 125 0x7D 7 'd 30 :RD = #1 8 'b < 15ae9 span class="hljs-number">01111110; // 126 0x7E 7 'd 31 :RD = #1 8 'b 01111110; // 126 0x7E 7 'd 32 :RD = #1 8 'b 01111111; // 127 0x7F 7 'd 33 :RD = #1 8 'b 01111110; // 126 0x7E 7 'd 34 :RD = #1 8 'b 01111110; // 126 0x7E 7 'd 35 :RD = #1 8 'b 01111101; // 125 0x7D 7 'd 36 :RD = #1 8 'b 01111100; // 124 0x7C 7 'd 37 :RD = #1 8 'b 01111011; // 123 0x7B 7 'd 38 :RD = #1 8 'b 01111001; // 121 0x79 7 'd 39 :RD = #1 8 'b 01110111; // 119 0x77 7 'd 40 :RD = #1 8 'b 01110101; // 117 0x75 7 'd 41 :RD = #1 8 'b 01110010; // 114 0x72 7 'd 42 :RD = #1 8 'b 01110000; // 112 0x70 7 'd 43 :RD = #1 8 'b 01101100; // 108 0x6C 7 'd 44 :RD = #1 8 'b 01101001; // 105 0x69 7 'd 45 :RD = #1 8 'b 01100110; // 102 0x66 7 'd 46 :RD = #1 8 'b 01100010; // 98 0x62 7 'd 47 :RD = #1 8 'b 01011110; // 94 0x5E 7 'd 48 :RD = #1 8 'b 01011001; // 89 0x59 7 'd 49 :RD = #1 8 'b 01010101; // 85 0x55 7 'd 50 :RD = #1 8 'b 01010000; // 80 0x50 7 'd 51 :RD = #1 8 'b 01001011; // 75 0x4B 7 'd 52 :RD = #1 8 'b 01000110; // 70 0x46 7 'd 53 :RD = #1 8 'b 01000001; // 65 0x41 7 'd 54 :RD = #1 8 'b 00111011; // 59 0x3B 7 'd 55 :RD = #1 8 'b 00110110; // 54 0x36 7 'd 56 :RD = #1 8 'b 00110000; // 48 0x30 7 'd 57 :RD = #1 8 'b 00101010; // 42 0x2A 7 'd 58 :RD = #1 8 'b 00100100; // 36 0x24 7 'd 59 :RD = #1 8 'b 00011110; // 30 0x1E 7 'd 60 :RD = #1 8 'b 00011000; // 24 0x18 7 'd 61 :RD = #1 8 'b 00010010; // 18 0x12 7 'd 62 :RD = #1 8 'b 00001100; // 12 0xC 7 'd 63 :RD = #1 8 'b 00000110; // 6 0x6 7 'd 64 :RD = #1 8 'b 00000000; // 0 0x0 7 'd 65 :RD = #1 8 'b 11111010; // -6 0xFA 7 'd 66 :RD = #1 8 'b 11110100; // -12 0xF4 7 'd 67 :RD = #1 8 'b 11101110; // -18 0xEE 7 'd 68 :RD = #1 8 'b 11101000; // -24 0xE8 7 'd 69 :RD = #1 8 'b 11100010; // -30 0xE2 7 'd 70 :RD = #1 8 'b 11011100; // -36 0xDC 7 'd 71 :RD = #1 8 'b 11010110; // -42 0xD6 7 'd 72 :RD = #1 8 'b 11010000; // -48 0xD0 7 'd 73 :RD = #1 8 'b 11001010; // -54 0xCA 7 'd 74 :RD = #1 8 'b 11000101; // -59 0xC5 7 'd 75 :RD = #1 8 'b 10111111; // -65 0xBF 7 'd 76 :RD = #1 8 'b 10111010; // -70 0xBA 7 'd 77 :RD = #1 8 'b 10110101; // -75 0xB5 7 'd 78 :RD = #1 8 'b 10110000; // -80 0xB0 7 'd 79 :RD = #1 8 'b 10101011; // -85 0xAB 7 'd 80 :RD = #1 8 'b 10100111; // -89 0xA7 7 'd 81 :RD = #1 8 'b 10100010; // -94 0xA2 7 'd 82 :RD = #1 8 'b 10011110; // -98 0x9E 7 'd 83 :RD = #1 8 'b 10011010; // -102 0x9A 7 'd 84 :RD = #1 8 'b 10010111; // -105 0x97 7 'd 85 :RD = #1 8 'b 10010100; // -108 0x94 7 'd 86 :RD = #1 8 'b 10010000; // -112 0x90 7 'd 87 :RD = #1 8 'b 10001110; // -114 0x8E 7 'd 88 :RD = #1 8 'b 10001011; // -117 0x8B 7 'd 89 :RD = #1 8 'b 10001001; // -119 0x89 7 'd 90 :RD = #1 8 'b 10000111; // -121 0x87 7 'd 91 :RD = #1 8 'b 10000101; // -123 0x85 7 'd 92 :RD = #1 8 'b 10000100; // -124 0x84 7 'd 93 :RD = #1 8 'b 10000011; // -125 0x83 7 'd 94 :RD = #1 8 'b 10000010; // -126 0x82 7 'd 95 :RD = #1 8 'b 10000010; // -126 0x82 7 'd 96 :RD = #1 8 'b 10000001; // -127 0x81 7 'd 97 :RD = #1 8 'b 10000010; // -126 0x82 7 'd 98 :RD = #1 8 'b 10000010; // -126 0x82 7 'd 99 :RD = #1 8 'b 10000011; // -125 0x83 7 'd 100 :RD = #1 8 'b 10000100; // -124 0x84 7 'd 101 :RD = #1 8 'b 10000101; // -123 0x85 7 'd 102 :RD = #1 8 'b 10000111; // -121 0x87 7 'd 103 :RD = #1 8 'b 10001001; // -119 0x89 7 'd 104 :RD = #1 8 'b 10001011; // -117 0x8B 7 'd 105 :RD = #1 8 'b 10001110; // -114 0x8E 7 'd 106 :RD = #1 8 'b 10010000; // -112 0x90 7 'd 107 :RD = #1 8 'b 10010100; // -108 0x94 7 'd 108 :RD = #1 8 'b 10010111; // -105 0x97 7 'd 109 :RD = #1 8 'b 10011010; // -102 0x9A 7 'd 110 :RD = #1 8 'b 10011110; // -98 0x9E 7 'd 111 :RD = #1 8 'b 10100010; // -94 0xA2 7 'd 112 :RD = #1 8 'b 10100111; // -89 0xA7 7 'd 113 :RD = #1 8 'b 10101011; // -85 0xAB 7 'd 114 :RD = #1 8 'b 10110000; // -80 0xB0 7 'd 115 :RD = #1 8 'b 10110101; // -75 0xB5 7 'd 116 :RD = #1 8 'b 10111010; // -70 0xBA 7 'd 117 :RD = #1 8 'b 10111111; // -65 0xBF 7 'd 118 :RD = #1 8 'b 11000101; // -59 0xC5 7 'd 119 :RD = #1 8 'b 11001010; // -54 0xCA 7 'd 120 :RD = #1 8 'b 11010000; // -48 0xD0 7 'd 121 :RD = #1 8 'b 11010110; // -42 0xD6 7 'd 122 :RD = #1 8 'b 11011100; // -36 0xDC 7 'd 123 :RD = #1 8 'b 11100010; // -30 0xE2 7 'd 124 :RD = #1 8 'b 11101000; // -24 0xE8 7 'd 125 :RD = #1 8 'b 11101110; // -18 0xEE 7 'd 126 :RD = #1 8 'b 11110100; // -12 0xF4 7 'd 127 :RD = #1 8 'b 11111010; // -6 0xFA default : RD = #1 0; endcase endmodule
②BDF原理图
③RTL结构图
计数器RTL结构图
ROM RTL结构图
④SignalTap仿真图
当计数器值为3时
当计数器的值为7时
当计数器的值为15时
⑤问题解答
拨动开关观察不同频率的正弦波，得到的正弦波频率与计数器增量值的对应关系是？
答：随着计数值的增加，正弦波频率也增加
其中能得到的最低频率的正弦波是多少？设该频率为 f1
答：正弦波信号一个周期采样128点，电路的工作时钟为50MHz，即是采样周期为0.02s
所以 f1=1128∗0.02∗10−6=0.39MHz
能有什么方法得到比F1频率还低的正弦波
答：增加计数值
实验要求2
把计数器进行改动，修改计数增量信号为10比特，计数值信号为10bit把计数值信号的高7位分配为ROM的地址，低3位悬空不使用
①Verilog HDL代码
修改后的计数器代码
module cnt_incr10( CLK , // clock INCR , // counter increase value CNTVAL); // counter value input CLK; input [10-1:0] INCR; output [10-1:0] CNTVAL; reg [10-1:0] CNTVAL; always @ (posedge CLK) begin CNTVAL <= INCR + CNTVAL; end endmodule // module cnt_incr10
只将计数器的高7位地址输入给ROM
②采用文件的形式指派管脚
to,location # 50MHz clock_input CLOCK_50 , PIN_G21 CLOCK_50_2 , PIN_B21 #slide switch[0] to slide switch[9] SW[0] , PIN_J6 SW[1] , PIN_H5 SW[2] , PIN_H6 SW[3] , PIN_G4 SW[4] , PIN_G5 SW[5] , PIN_J7 SW[6] , PIN_H7 SW[7] , PIN_E3 SW[8] , PIN_E4 SW[9] , PIN_D2
③BDF原理图
④RTL结构图
计数器的RTL结构图
⑤SignalTap
可以看出最低频率f1变为
f1=11024∗0.02∗10−6=0.049MHz
DDS（直接数字频率合成电路）
其输出信号频率 f1、电路工作时钟频率 fh、计数器增量值 M 和计数器数据位宽 N之间的表达式关系为：f1=M2N∗fh
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