【iCore1S 双核心板_FPGA】例程三：计数器实验——计数器的使用

//--------------------Module_counter------------------//
module counter(
input clk_12m,
output fpga_ledr
);

//-----------------------rst_n------------------------//
reg rst_n;
reg [3:0]cnt_rst;

always@(posedge clk_12m)
begin
if(cnt_rst == 4'd10)
begin
rst_n <= 1'd1;
cnt_rst <= 4'd10;
end
else cnt_rst <= cnt_rst + 1'd1;
end

//-----------------------led-------------------------//
reg [19:0]cnt_led;
reg led;

always@(posedge clk_12m or negedge rst_n)
begin
if(!rst_n)
begin
cnt_led <= 20'd0;
led <=1'd1;
end
else if(cnt_led == 20'd1000000)
begin
led <= ~led;
cnt_led  <= 20'd0;
end
else cnt_led <= cnt_led + 1'd1;
end

assign fpga_ledr = led;

//------------------------endmodule------------------//
endmodule