aa

`timescale 1ns/1ps

module speed_select(
clk,rst,
bps_start,clk_bps,
);

input clk;	//主时钟是  50MHZ
input rst;
input bps_start;
output clk_bps;

/*
parameter 		bps9600 	= 5207,	//波特率为9600bps
bps19200 	= 2603,	//波特率为19200bps
bps38400 	= 1301,	//波特率为38400bps
bps57600 	= 867,	//波特率为57600bps
bps115200	= 433;	//波特率为115200bps

parameter 		bps9600_2 	= 2603,
bps19200_2	= 1301,
bps38400_2	= 650,
bps57600_2	= 433,
bps115200_2 = 216;
*/

`define BPS_PARA   5207 // 相对于  50MHZ 分频，波特率为 9600
`define BPS_PARA_HF 2603 //9600 一半

reg[12:0] cnt;		//分频计数
reg clk_bps_r;		//波特率时钟寄存器

reg[2:0] uart_ctrl;		// uart波特率选择寄存器

always @ (posedge clk or negedge rst)
if(!rst) cnt <= 13'd0;
else if((cnt == `BPS_PARA ) || !bps_start) cnt <= 13'd0; //波特率计数清零。
else cnt <= cnt + 1'b1;

always @ (posedge clk or negedge rst)
if(!rst) clk_bps_r <= 1'b0;
else if(cnt == `BPS_PARA_HF) clk_bps_r <= 1'b1;
else clk_bps_r <= 1'b0;

assign clk_bps = clk_bps_r;

endmodule