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Chisel实验笔记(三)

2015-05-29 11:59 190 查看
在《Chisel实验笔记(一)》中我们得到了verilog文件,在《Chisel实验笔记(二)》中我们使用Icarus Verilog、GtkWave对的道德verilog文件进行了仿真测试,实际上,时欧诺个Chisel可以得到对应的C++文件,从而可以直接进行仿真,本文就介绍产生C++文件,进行测试的实验过程。

1、修改Max2.scala文件如下:

import Chisel._

class Max2 extends Module {
val io = new Bundle {
val in0 = UInt(INPUT,  8)
val in1 = UInt(INPUT,  8)
val out = UInt(OUTPUT, 8)
}
io.out := Mux(io.in0 > io.in1, io.in0, io.in1)

}

class Max2Tests(c: Max2) extends Tester(c) {
for (i <- 0 until 10) {
// FILL THIS IN HERE
val in0 = rnd.nextInt(1 << 8)
val in1 = rnd.nextInt(1 << 8)
poke(c.io.in0, in0)
poke(c.io.in1, in1)
// FILL THIS IN HERE
step(1)
expect(c.io.out, if(in0 > in1) in0 else in1)
}
}

object max2 {
def main(args: Array[String]) : Unit={
val margs=Array("--backend","c","--genHarness","--compile","--test")
chiselMainTest(margs, () => Module(new Max2())){c => new Max2Tests(c)}
}
}
相比《Chisel实验笔记(一)》中的Max2.scala代码,其中增加了Max2Tests类,这是专门用来测试的,相当于verilog中的testbench,在这个Max2Test类中,进行了10次循环,每次测试,都随机得到两个8位的数,使用poke将这两个随机数分别赋值给Max2的in0、in1,然后使用expect判断Max2的输出out是否是是in0、in1中较大的那个值。

除了增加Max2Test类,还修改了main中的margs,将其中的“v”改为了“c”,还增加了参数“--genHarness”、“--test”。

然后打开终端,进入chisel_max的目录,输入sbt,再输入run,可以得到如下结果:

> run
[info] Compiling 1 Scala source to /home/riscv/Documents/chisel_max/target/scala-2.10/classes...
[warn] there were 8 feature warning(s); re-run with -feature for details
[warn] one warning found
[info] Running max2
CPP elaborate
[info] [0.025] // COMPILING < (class Max2)>(0)
[info] [0.028] giving names
[info] [0.034] executing custom transforms
[info] [0.034] adding clocks and resets
[info] [0.038] inferring widths
[info] [0.042] checking widths
[info] [0.043] lowering complex nodes to primitives
[info] [0.043] removing type nodes
[info] [0.043] compiling 5 nodes
[info] [0.044] computing memory ports
[info] [0.044] resolving nodes to the components
[info] [0.049] creating clock domains
[info] [0.050] pruning unconnected IOs
[info] [0.051] checking for combinational loops
[info] [0.052] NO COMBINATIONAL LOOP FOUND
[info] [0.058] populating clock domains
CppBackend::elaborate: need 0, redundant 0 shadow registers
[info] [0.067] generating cpp files
CppBackend: createCppFile Max2.cpp
[info] [1.729] g++ -c -o ./Max2-emulator.o  -I../ -Inull/csrc/  ./Max2-emulator.cpp RET 0
[info] [2.155] g++ -c -o ./Max2.o  -I../ -Inull/csrc/  ./Max2.cpp RET 0
[info] [2.302] g++  -o ./Max2 ./Max2.o ./Max2-emulator.o RET 0
SEED 1432871199400
STARTING ./Max2
RESET 5
POKE Max2.io_in0 <-  0x6b
POKE Max2.io_in1 <-  0x99
STEP 1 -> 1
PEEK Max2.io_out -> 0x99
EXPECT Max2.io_out <- 153 == 153 PASS
POKE Max2.io_in0 <-  0xc
POKE Max2.io_in1 <-  0xa7
STEP 1 -> 2
PEEK Max2.io_out -> 0xa7
EXPECT Max2.io_out <- 167 == 167 PASS
POKE Max2.io_in0 <-  0x51
POKE Max2.io_in1 <-  0x80
STEP 1 -> 3
PEEK Max2.io_out -> 0x80
EXPECT Max2.io_out <- 128 == 128 PASS
POKE Max2.io_in0 <-  0xc7
POKE Max2.io_in1 <-  0x8f
STEP 1 -> 4
PEEK Max2.io_out -> 0xc7
EXPECT Max2.io_out <- 199 == 199 PASS
POKE Max2.io_in0 <-  0x21
POKE Max2.io_in1 <-  0x60
STEP 1 -> 5
PEEK Max2.io_out -> 0x60
EXPECT Max2.io_out <- 96 == 96 PASS
POKE Max2.io_in0 <-  0xd6
POKE Max2.io_in1 <-  0xaf
STEP 1 -> 6
PEEK Max2.io_out -> 0xd6
EXPECT Max2.io_out <- 214 == 214 PASS
POKE Max2.io_in0 <-  0x96
POKE Max2.io_in1 <-  0x98
STEP 1 -> 7
PEEK Max2.io_out -> 0x98
EXPECT Max2.io_out <- 152 == 152 PASS
POKE Max2.io_in0 <-  0xa4
POKE Max2.io_in1 <-  0x6b
STEP 1 -> 8
PEEK Max2.io_out -> 0xa4
EXPECT Max2.io_out <- 164 == 164 PASS
POKE Max2.io_in0 <-  0xe6
POKE Max2.io_in1 <-  0x6c
STEP 1 -> 9
PEEK Max2.io_out -> 0xe6
EXPECT Max2.io_out <- 230 == 230 PASS
POKE Max2.io_in0 <-  0x7b
POKE Max2.io_in1 <-  0x3c
STEP 1 -> 10
PEEK Max2.io_out -> 0x7b
EXPECT Max2.io_out <- 123 == 123 PASS
RAN 10 CYCLES PASSED
PASSED
[success] Total time: 3 s, completed May 29, 2015 11:46:41 AM


在终端中输出了10次模拟结果,PASS表示通过测试。
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