stm32F4的NVIC和中断
2015-04-26 17:02
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ARMv7-M provides an interrupt controller as an integral part of the ARMv7-M exception model.
ARMv7-M supports level-sensitivie and pulse-sensitive interrupt behavior.
Pulse interrupt sources must be held long enough to be sampled reliably by the processor clock to ensure they are lated and become pending. Pulses held for a clokc period act linke edge-sensitive interrupts. These can become pending again while the interrupt
is active.
level-based interrupts becomes pending, and then make the interrupt active. The interrupt Service Routine then acesses the peripheral, causing it to seassert the interrupt. If the interrupt is still asserted on return from the ISR, it becomes pending again.
The NVIC supports the following features:
• NVIC interrupts can be enabled and disabled by writing to their corresponding Interrupt Set-Enable or Interrupt Clear-Enable register bit-field. The registers use a write-1-to-enable
and write-1-to-clear policy, both registers reading back the current enabled state of the corresponding (32) interrupts.
When an interrupt is disabled, interrupt assertion causes the interrupt to become pending, but the interrupt cannot become active. If an interrupt is active when it is disabled, it remains in the active state until this is cleared
by a reset or an exception return. Clearing the enable bit prevents any new activation of the associated interrupt.
An implementation can hard-wire interrupt enable bits to zero if the associated interrupt line does not exist,or hard-wired them to one if the associated interrupt line cannot be disabled.
• Software can set or remove the pending state of NVIC interrupts using a complementary pair of registers, the Set-Pending Register and Clear-Pending Register. The registers use
a write-one-to-enable and write-one-to-clear policy, and a read of either register returns the current pending state of the corresponding 32 interrupts. Writing
1 to a bit in the Clear-Pending Register has no effect on the execution status of an active interrupt. It is IMPLEMENTATION DEFINED for each interrupt line supported, whether an interrupt supports either or both setting
and clearing of the associated pending state under software control.
• Active bit status is provided to enable software to determine whether an interrupt is inactive, active, pending,
or active and pending.
The following are registers related to NVIC.
Interrupt Controller Type register, ICTR
Purpose shows the number of interrupt that the NVIC supports.
The total number of interrupt lines supported by an implementation, defined in groups of 32. That is, the total number of interrupt lines is up to (32*(INTLINESNUM+1)). However, the absolute maximum number of interrupts is 496, corresponding
to the INTLINESNUM value 0b1111.
Cortex-M4 support a maximum of 240 external interrupts, so the absolute maximum number for it is b0111
Software Triggered Interrupt Register, STIR
Purpose: Provides a mechanism for software to generate an interrupt.
Usage constraints: This register applies to implemented external interrupts only.
INTID, bits[8:0]: Indicates the interrupt to be triggered. The value written is (ExceptionNumber - 16).
Interrupt Set-Enable Registers, NVIC_ISER0-NVIC_ISER15
Purpose: Enables, or reads the enable state of a group of interrupts.
Usage constraints NVIC_ISERn[31:0] are the set-enable bits for interrupts (31+(32*n)) - (32*n). When n=15, bits[31:16] are reserved.
SETENA, bits[m] For register NVIC_ISERn, enables or shows the current enabled state of interrupt (m+(32*n)):
0 On reads, interrupt disabled.
On writes, no effect.
1 On reads, interrupt enabled.
On writes, enable interrupt.
m takes the values from 31 to 0, except for NVIC_ISER15, where:
• m takes the values from 15 to 0.
• Register bits[31:16] are reserved, RAZ/WI.
Software can enable multiple interrupts in a single write to NVIC_ISERn.
Interrupt Clear-Enable Registers, NVIC_ICER0-NVIC_ICER15
Purpose: Disables, or reads the enable state of, a group of registers.
Usage constraints: NVIC_ICERn[31:0] are the clear-enable bits for interrupts (31+(32*n)) - (32*n). When n=15, bits[31:16] are reserved.
CLRENA, bits[m] For register NVIC_ICERn, disables or shows the current enabled state of interrupt (m+(32*n)):
0 On reads, interrupt disabled.
On writes, no effect.
1 On reads, interrupt enabled.
On writes, disable interrupt.
m takes the values from 31 to 0, except for NVIC_ICER15, where:
• m takes the values from 15 to 0.
• Register bits[31:16] are reserved, RAZ/WI.
Software can disable multiple interrupts in a single write to NVIC_ICERn.
Interrupt Set-Pending Registers, NVIC_ISPR0-NVIC_ISPR15
Purpose: For a group of interrupts, changes interrupt status to pending, or shows the current pending status.
Interrupt Clear-Pending Registers, NVIC_ICPR0-NVIC_ICPR15
Purpose: For a group of interrupts, clears the interrupt pending status, or shows the current pending status.
note: The ways to set these registers are similar to the ways to set NVIC_ISER and NVIC_ICER. So detailed descriptions are omitted in this blog.
Interrupt Active Bit Registers, NVIC_IABR0-NVIC_IABR15
Purpose: For a group of 32 interrupts, shows whether each interrupt is active.
ACTIVE, bits[m] For register NVIC_IABRn, shows whether interrupt (m+(32*n)) is active:
0 Interrupt not active.
1 Interrupt active.
m takes the values from 31 to 0, except for NVIC_IABR15, where:
• m takes the values from 15 to 0.
• Register bits[31:16] are reserved, RAZ/WI.
Interrupt Priority Registers, NVIC_IPR0-NVIC_IPR123
Purpose: Sets or reads interrupt priorities.
PRI_N3, bits[31:24] For register NVIC_IPRn, priority of interrupt number 4n+3.
PRI_N2, bits[23:16] For register NVIC_IPRn, priority of interrupt number 4n+2.
PRI_N1, bits[15:8] For register NVIC_IPRn, priority of interrupt number 4n+1.
PRI_N0, bits[7:0] For register NVIC_IPRn, priority of interrupt number 4n.
the downward description are specific for stm32 external interrupt/event controller.
External interrupt/event controller (EXTI)
The external interrupt/event controller consists of up to 23 edge detectors for generating event/interrupt requests. Each input line can be independently configured to select the type (interrupt
or event) and the corresponding trigger event (rising or falling or both). Each line can also masked independently. A pending register maintains the status line of the
interrupt requests.
The main features are the following:
• independent trigger and mask on each interrupt/event line
• dedicated status bit for each interrupt line
• generation of up to 23 software event/interrupt requests
• detection of external signals with a pulse width lower than the APB2 clock period. Refer to the electrical characteristics section of the STM32F4xx datasheets for details on this parameter.
the stm32 document also described the procedure of setting up an interrupt or an event.
Hardware interrupt selection
To configure the 23 lines as interrupt sources, use the following procedure:
• Configure the mask bits of the 23 interrupt lines (EXTI_IMR)
• Configure the Trigger selection bits of the interrupt lines (EXTI_RTSR and EXTI_FTSR)
• Configure the enable and mask bits that control the NVIC IRQ channel mapped to the external interrupt controller (EXTI) so that an interrupt coming from one of the 23 lines can be correctly acknowledged.
Hardware event selection
To configure the 23 lines as event sources, use the following procedure:
• Configure the mask bits of the 23 event lines (EXTI_EMR)
• Configure the Trigger selection bits of the event lines (EXTI_RTSR and EXTI_FTSR)
Software interrupt/event selection
The 23 lines can be configured as software interrupt/event lines. The following is the procedure to generate a software interrupt.
• Configure the mask bits of the 23 interrupt/event lines (EXTI_IMR, EXTI_EMR)
• Set the required bit in the software interrupt register (EXTI_SWIER)
Interrupt mask register (EXTI_IMR)
Bits 31:23 Reserved, must be kept at reset value.
Bits 22:0 MRx: Interrupt mask on line x
0: Interrupt request from line x is masked
1: Interrupt request from line x is not masked
Event mask register (EXTI_EMR)
Bits 31:23 Reserved, must be kept at reset value.
Bits 22:0 MRx: Event mask on line x
0: Event request from line x is masked
1: Event request from line x is not masked
Rising trigger selection register (EXTI_RTSR)
Bits 31:23 Reserved, must be kept at reset value.
Bits 22:0 TRx: Rising trigger event configuration bit of line x
0: Rising trigger disabled (for Event and Interrupt) for input line
1: Rising trigger enabled (for Event and Interrupt) for input line
Falling trigger selection register (EXTI_FTSR)
Bits 31:23 Reserved, must be kept at reset value.
Bits 22:0 TRx: Falling trigger event configuration bit of line x
0: Falling trigger disabled (for Event and Interrupt) for input line
1: Falling trigger enabled (for Event and Interrupt) for input line.
Software interrupt event register (EXTI_SWIER)
Bits 31:23 Reserved, must be kept at reset value.
Bits 22:0 SWIERx: Software Interrupt on line x
If interrupt are enabled on line x in the EXTI_IMR register, writing '1' to SWIERx bit when it is set at '0' sets the corresponding pending bit in the EXTI_PR register, thus resulting in an interrupt request generation. This
bit is cleared by clearing the corresponding bit in EXTI_PR (by writing a 1 to the bit).
Pending register (EXTI_PR)
Bits 31:23 Reserved, must be kept at reset value.
Bits 22:0 PRx: Pending bit
0: No trigger request occurred
1: selected trigger request occurred
This bit is set when the selected edge event arrives on the external interrupt line. This bit is cleared by programming it to ‘1’.
In addition to these configurations, we also need to connect EXTI Lines to the corrected pins, using external interrupt configuration register.
There are four of these registers and each is responsible for 4 EXTI lines. And each EXTI line is also connected to a corresponding pin. And which GPIO is used is defined by the value in theses registers. For example, when we need to enable the interrupt
of PA2. we should to write the 0000 to the EXIT3 field in the SYSCFG_EXTICR1.
I only put one register map in this blog.
SYSCFG external interrupt configuration register 1
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 EXTIx[3:0]: EXTI x configuration (x = 0 to 3)
These bits are written by software to select the source input for the EXTIx external interrupt.
0000: PA[x] pin
0001: PB[x] pin
0010: PC[x] pin
0011: PD[x] pin
0100: PE[x] pin
0101: PF[x] pin
0110: PG[x] pin
0111: PH[x] pin
1000: PI[x] pin
依据说明中的流程下面将说明一下stm32库中的开启中断的步骤和库的实现
•在开启中断之前我们必须配置相关的GPIO pin为输入。
•连接EXTI line和相关pin口
• Configure the mask bits of the 23 interrupt lines (EXTI_IMR)
• Configure the Trigger selection bits of the interrupt lines (EXTI_RTSR and EXTI_FTSR)
• Configure the enable and mask bits that control the NVIC IRQ channel mapped to the external interrupt controller (EXTI) so that an interrupt coming from one of the 23
lines can be correctly acknowledged.
在stm32f4xx_it.c(例程中专门用来放函数的源文件)实现了对应的EXTI0外部中断线的中断函数。功能为检查pending，之后开合LED4，注意外部中断清中断时应当清楚外部中断的pending bit。
ARMv7-M supports level-sensitivie and pulse-sensitive interrupt behavior.
Pulse interrupt sources must be held long enough to be sampled reliably by the processor clock to ensure they are lated and become pending. Pulses held for a clokc period act linke edge-sensitive interrupts. These can become pending again while the interrupt
is active.
level-based interrupts becomes pending, and then make the interrupt active. The interrupt Service Routine then acesses the peripheral, causing it to seassert the interrupt. If the interrupt is still asserted on return from the ISR, it becomes pending again.
The NVIC supports the following features:
• NVIC interrupts can be enabled and disabled by writing to their corresponding Interrupt Set-Enable or Interrupt Clear-Enable register bit-field. The registers use a write-1-to-enable
and write-1-to-clear policy, both registers reading back the current enabled state of the corresponding (32) interrupts.
When an interrupt is disabled, interrupt assertion causes the interrupt to become pending, but the interrupt cannot become active. If an interrupt is active when it is disabled, it remains in the active state until this is cleared
by a reset or an exception return. Clearing the enable bit prevents any new activation of the associated interrupt.
An implementation can hard-wire interrupt enable bits to zero if the associated interrupt line does not exist,or hard-wired them to one if the associated interrupt line cannot be disabled.
• Software can set or remove the pending state of NVIC interrupts using a complementary pair of registers, the Set-Pending Register and Clear-Pending Register. The registers use
a write-one-to-enable and write-one-to-clear policy, and a read of either register returns the current pending state of the corresponding 32 interrupts. Writing
1 to a bit in the Clear-Pending Register has no effect on the execution status of an active interrupt. It is IMPLEMENTATION DEFINED for each interrupt line supported, whether an interrupt supports either or both setting
and clearing of the associated pending state under software control.
• Active bit status is provided to enable software to determine whether an interrupt is inactive, active, pending,
or active and pending.
The following are registers related to NVIC.
Interrupt Controller Type register, ICTR
Purpose shows the number of interrupt that the NVIC supports.
The total number of interrupt lines supported by an implementation, defined in groups of 32. That is, the total number of interrupt lines is up to (32*(INTLINESNUM+1)). However, the absolute maximum number of interrupts is 496, corresponding
to the INTLINESNUM value 0b1111.
Cortex-M4 support a maximum of 240 external interrupts, so the absolute maximum number for it is b0111
Software Triggered Interrupt Register, STIR
Purpose: Provides a mechanism for software to generate an interrupt.
Usage constraints: This register applies to implemented external interrupts only.
INTID, bits[8:0]: Indicates the interrupt to be triggered. The value written is (ExceptionNumber - 16).
Interrupt Set-Enable Registers, NVIC_ISER0-NVIC_ISER15
Purpose: Enables, or reads the enable state of a group of interrupts.
Usage constraints NVIC_ISERn[31:0] are the set-enable bits for interrupts (31+(32*n)) - (32*n). When n=15, bits[31:16] are reserved.
SETENA, bits[m] For register NVIC_ISERn, enables or shows the current enabled state of interrupt (m+(32*n)):
0 On reads, interrupt disabled.
On writes, no effect.
1 On reads, interrupt enabled.
On writes, enable interrupt.
m takes the values from 31 to 0, except for NVIC_ISER15, where:
• m takes the values from 15 to 0.
• Register bits[31:16] are reserved, RAZ/WI.
Software can enable multiple interrupts in a single write to NVIC_ISERn.
Interrupt Clear-Enable Registers, NVIC_ICER0-NVIC_ICER15
Purpose: Disables, or reads the enable state of, a group of registers.
Usage constraints: NVIC_ICERn[31:0] are the clear-enable bits for interrupts (31+(32*n)) - (32*n). When n=15, bits[31:16] are reserved.
CLRENA, bits[m] For register NVIC_ICERn, disables or shows the current enabled state of interrupt (m+(32*n)):
0 On reads, interrupt disabled.
On writes, no effect.
1 On reads, interrupt enabled.
On writes, disable interrupt.
m takes the values from 31 to 0, except for NVIC_ICER15, where:
• m takes the values from 15 to 0.
• Register bits[31:16] are reserved, RAZ/WI.
Software can disable multiple interrupts in a single write to NVIC_ICERn.
Interrupt Set-Pending Registers, NVIC_ISPR0-NVIC_ISPR15
Purpose: For a group of interrupts, changes interrupt status to pending, or shows the current pending status.
Interrupt Clear-Pending Registers, NVIC_ICPR0-NVIC_ICPR15
Purpose: For a group of interrupts, clears the interrupt pending status, or shows the current pending status.
note: The ways to set these registers are similar to the ways to set NVIC_ISER and NVIC_ICER. So detailed descriptions are omitted in this blog.
Interrupt Active Bit Registers, NVIC_IABR0-NVIC_IABR15
Purpose: For a group of 32 interrupts, shows whether each interrupt is active.
ACTIVE, bits[m] For register NVIC_IABRn, shows whether interrupt (m+(32*n)) is active:
0 Interrupt not active.
1 Interrupt active.
m takes the values from 31 to 0, except for NVIC_IABR15, where:
• m takes the values from 15 to 0.
• Register bits[31:16] are reserved, RAZ/WI.
Interrupt Priority Registers, NVIC_IPR0-NVIC_IPR123
Purpose: Sets or reads interrupt priorities.
PRI_N3, bits[31:24] For register NVIC_IPRn, priority of interrupt number 4n+3.
PRI_N2, bits[23:16] For register NVIC_IPRn, priority of interrupt number 4n+2.
PRI_N1, bits[15:8] For register NVIC_IPRn, priority of interrupt number 4n+1.
PRI_N0, bits[7:0] For register NVIC_IPRn, priority of interrupt number 4n.
the downward description are specific for stm32 external interrupt/event controller.
External interrupt/event controller (EXTI)
The external interrupt/event controller consists of up to 23 edge detectors for generating event/interrupt requests. Each input line can be independently configured to select the type (interrupt
or event) and the corresponding trigger event (rising or falling or both). Each line can also masked independently. A pending register maintains the status line of the
interrupt requests.
The main features are the following:
• independent trigger and mask on each interrupt/event line
• dedicated status bit for each interrupt line
• generation of up to 23 software event/interrupt requests
• detection of external signals with a pulse width lower than the APB2 clock period. Refer to the electrical characteristics section of the STM32F4xx datasheets for details on this parameter.
the stm32 document also described the procedure of setting up an interrupt or an event.
Hardware interrupt selection
To configure the 23 lines as interrupt sources, use the following procedure:
• Configure the mask bits of the 23 interrupt lines (EXTI_IMR)
• Configure the Trigger selection bits of the interrupt lines (EXTI_RTSR and EXTI_FTSR)
• Configure the enable and mask bits that control the NVIC IRQ channel mapped to the external interrupt controller (EXTI) so that an interrupt coming from one of the 23 lines can be correctly acknowledged.
Hardware event selection
To configure the 23 lines as event sources, use the following procedure:
• Configure the mask bits of the 23 event lines (EXTI_EMR)
• Configure the Trigger selection bits of the event lines (EXTI_RTSR and EXTI_FTSR)
Software interrupt/event selection
The 23 lines can be configured as software interrupt/event lines. The following is the procedure to generate a software interrupt.
• Configure the mask bits of the 23 interrupt/event lines (EXTI_IMR, EXTI_EMR)
• Set the required bit in the software interrupt register (EXTI_SWIER)
Interrupt mask register (EXTI_IMR)
Bits 31:23 Reserved, must be kept at reset value.
Bits 22:0 MRx: Interrupt mask on line x
0: Interrupt request from line x is masked
1: Interrupt request from line x is not masked
Event mask register (EXTI_EMR)
Bits 31:23 Reserved, must be kept at reset value.
Bits 22:0 MRx: Event mask on line x
0: Event request from line x is masked
1: Event request from line x is not masked
Rising trigger selection register (EXTI_RTSR)
Bits 31:23 Reserved, must be kept at reset value.
Bits 22:0 TRx: Rising trigger event configuration bit of line x
0: Rising trigger disabled (for Event and Interrupt) for input line
1: Rising trigger enabled (for Event and Interrupt) for input line
Falling trigger selection register (EXTI_FTSR)
Bits 31:23 Reserved, must be kept at reset value.
Bits 22:0 TRx: Falling trigger event configuration bit of line x
0: Falling trigger disabled (for Event and Interrupt) for input line
1: Falling trigger enabled (for Event and Interrupt) for input line.
Software interrupt event register (EXTI_SWIER)
Bits 31:23 Reserved, must be kept at reset value.
Bits 22:0 SWIERx: Software Interrupt on line x
If interrupt are enabled on line x in the EXTI_IMR register, writing '1' to SWIERx bit when it is set at '0' sets the corresponding pending bit in the EXTI_PR register, thus resulting in an interrupt request generation. This
bit is cleared by clearing the corresponding bit in EXTI_PR (by writing a 1 to the bit).
Pending register (EXTI_PR)
Bits 31:23 Reserved, must be kept at reset value.
Bits 22:0 PRx: Pending bit
0: No trigger request occurred
1: selected trigger request occurred
This bit is set when the selected edge event arrives on the external interrupt line. This bit is cleared by programming it to ‘1’.
In addition to these configurations, we also need to connect EXTI Lines to the corrected pins, using external interrupt configuration register.
There are four of these registers and each is responsible for 4 EXTI lines. And each EXTI line is also connected to a corresponding pin. And which GPIO is used is defined by the value in theses registers. For example, when we need to enable the interrupt
of PA2. we should to write the 0000 to the EXIT3 field in the SYSCFG_EXTICR1.
I only put one register map in this blog.
SYSCFG external interrupt configuration register 1
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 EXTIx[3:0]: EXTI x configuration (x = 0 to 3)
These bits are written by software to select the source input for the EXTIx external interrupt.
0000: PA[x] pin
0001: PB[x] pin
0010: PC[x] pin
0011: PD[x] pin
0100: PE[x] pin
0101: PF[x] pin
0110: PG[x] pin
0111: PH[x] pin
1000: PI[x] pin
依据说明中的流程下面将说明一下stm32库中的开启中断的步骤和库的实现
•在开启中断之前我们必须配置相关的GPIO pin为输入。
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN; GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0; GPIO_Init(GPIOA, &GPIO_InitStructure);GPIO_Init()将设置GPIOA的MODER为input，SPEED，然后PuPd为无上下拉电阻。
•连接EXTI line和相关pin口
SYSCFG_EXTILineConfig(EXTI_PortSourceGPIOA, EXTI_PinSource0);它将设置SYSCFG
void SYSCFG_EXTILineConfig(uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex)
{
uint32_t tmp = 0x00;
/* Check the parameters */
assert_param(IS_EXTI_PORT_SOURCE(EXTI_PortSourceGPIOx));
assert_param(IS_EXTI_PIN_SOURCE(EXTI_PinSourcex));
tmp = ((uint32_t)0x0F) << (0x04 * (EXTI_PinSourcex & (uint8_t)0x03));
SYSCFG->EXTICR[EXTI_PinSourcex >> 0x02] &= ~tmp;
SYSCFG->EXTICR[EXTI_PinSourcex >> 0x02] |= (((uint32_t)EXTI_PortSourceGPIOx) << (0x04 * (EXTI_PinSourcex & (uint8_t)0x03)));
}• Configure the mask bits of the 23 interrupt lines (EXTI_IMR)
• Configure the Trigger selection bits of the interrupt lines (EXTI_RTSR and EXTI_FTSR)
/* Configure EXTI Line0 */ EXTI_InitStructure.EXTI_Line = EXTI_Line0; EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt; EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising; EXTI_InitStructure.EXTI_LineCmd = ENABLE; EXTI_Init(&EXTI_InitStructure);EXTI_Init()将设置EXTI_IMR，开启相关外部中断的mask bit， 设置EXTI_RTSR and/or EXTI_FTSR，来指定何种边沿触发中断。
• Configure the enable and mask bits that control the NVIC IRQ channel mapped to the external interrupt controller (EXTI) so that an interrupt coming from one of the 23
lines can be correctly acknowledged.
/* Enable and set EXTI Line0 Interrupt to the lowest priority */ NVIC_InitStructure.NVIC_IRQChannel = EXTI0_IRQn; NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0x01; NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0x01; NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; NVIC_Init(&NVIC_InitStructure);NVIC_Init()将设置NVIC相关的寄存器。
在stm32f4xx_it.c(例程中专门用来放函数的源文件)实现了对应的EXTI0外部中断线的中断函数。功能为检查pending，之后开合LED4，注意外部中断清中断时应当清楚外部中断的pending bit。
void EXTI0_IRQHandler(void)
{
if(EXTI_GetITStatus(EXTI_Line0) != RESET)
{
/* Toggle LED4 */
STM_EVAL_LEDToggle(LED4);
/* Clear the EXTI line 0 pending bit */
EXTI_ClearITPendingBit(EXTI_Line0);
}
}
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