ISE Simulator综合后仿真 - How do you run Post Synthesis Simulation in ISE Project Navigator?
2013-01-27 15:36
561 查看
转自:http://china.xilinx.com/support/answers/45668.htm
疑问描述
How do you run Post Synthesis Simulation in ISE Project Navigator?
解决方案
Follow these steps to run simulation:
Create the project in ISE Project Navigator and add all the required modules including the testbench.
Set the module (DUT) you want to perform Post-Synthesis Simulation as the Top Module.
Run Synthesis.
Once the design is synthesized. Expand the Synthesize -> XST option and double-click on Generate Post-Synthesis Simulation Model. This runs NetGen to create the simulation netlist. The output is placed in the "./netgen/synthesis" folder in
your project directory. The file generated is named: <top_module_name>_synthesis.vhd/v. This file would be a VHDL or Verilog file depending on the source file of the synthesized module. Alternately, you can right-click on Generate Post-Synthesis Simulation
Model and change the value of Simulation Model Target (VHDL/Verilog) as per your needs.
In your "project" directory, create a new ".prj" file. Add the two entries as shown below:
vhdl/verilog work (or library name) "netgen\synthesis\<top_module_name>_synthesis.vhd/v"
vhdl/verilog work (or library name) "testbench.vhd/v"
Open the ISE Design Suite Command Prompt and run the following commands (depending on simulation language):
Verilog: fuse -intstyle ise -incremental -lib unisims_ver -lib unimacro_ver -lib xilinxcorelib_ver -lib secureip -o x_synthesis.exe -prj new.prj work.<testbench> work.glbl
VHDL: fuse -intstyle ise -incremental -lib unisim -lib unimacro -lib xilinxcorelib -lib secureip -o x_synthesis.exe -prj new.prj work.<testbench>
Run the generated simulation executable x_synthesis.exe -gui to open ISIM GUI.
The outputted waveform is the Post-Synthesis Simulation for the design under test.
适用于
ISE Design Suite - 13.2
ISE Design Suite - 13.3
ISE Design Suite - 13.4
疑问描述
How do you run Post Synthesis Simulation in ISE Project Navigator?
解决方案
Create the project in ISE Project Navigator and add all the required modules including the testbench.
Set the module (DUT) you want to perform Post-Synthesis Simulation as the Top Module.
Run Synthesis.
Once the design is synthesized. Expand the Synthesize -> XST option and double-click on Generate Post-Synthesis Simulation Model. This runs NetGen to create the simulation netlist. The output is placed in the "./netgen/synthesis" folder in
your project directory. The file generated is named: <top_module_name>_synthesis.vhd/v. This file would be a VHDL or Verilog file depending on the source file of the synthesized module. Alternately, you can right-click on Generate Post-Synthesis Simulation
Model and change the value of Simulation Model Target (VHDL/Verilog) as per your needs.
In your "project" directory, create a new ".prj" file. Add the two entries as shown below:
vhdl/verilog work (or library name) "netgen\synthesis\<top_module_name>_synthesis.vhd/v"
vhdl/verilog work (or library name) "testbench.vhd/v"
Open the ISE Design Suite Command Prompt and run the following commands (depending on simulation language):
Verilog: fuse -intstyle ise -incremental -lib unisims_ver -lib unimacro_ver -lib xilinxcorelib_ver -lib secureip -o x_synthesis.exe -prj new.prj work.<testbench> work.glbl
VHDL: fuse -intstyle ise -incremental -lib unisim -lib unimacro -lib xilinxcorelib -lib secureip -o x_synthesis.exe -prj new.prj work.<testbench>
Run the generated simulation executable x_synthesis.exe -gui to open ISIM GUI.
The outputted waveform is the Post-Synthesis Simulation for the design under test.
适用于
设计工具
ISE Design Suite - 13.1ISE Design Suite - 13.2
ISE Design Suite - 13.3
ISE Design Suite - 13.4
相关文章推荐
- ISE Simulator综合后仿真 - How do you run Post Synthesis Simulation in ISE Project Navigator?
- How to run eclipse in clean mode? and what happens if we do so?
- Bubble Gum, Bubble Gum, in the dish, how many pieces do you wish?”
- JQuery怎么知道一个元素是否隐藏或显示How do you test if something is hidden in jQuery?
- How do you get the length of a string in jQuery?
- JQuery怎么知道一个元素是否隐藏或显示How do you test if something is hidden in jQuery?
- 2014-11-16:How to run java project(containing several package) in linux
- without inq or pp how do you find out what LUN / array a scsi device is
- JQuery怎么知道一个元素是否隐藏或显示How do you test if something is hidden in jQuery?
- RunningMapReduceExampleTFIDF - hadoop-clusternet - This document describes how to run the TF-IDF MapReduce example against ascii books. - This project is for those who wants to experiment hadoop as a skunkworks in a small cluster (1-10 nodes) - Google Pro
- JQuery怎么知道一个元素是否隐藏或显示How do you test if something is hidden in jQuery?
- RunningMapReduceExampleTFIDF - hadoop-clusternet - This document describes how to run the TF-IDF MapReduce example against ascii books. - This project is for those who wants to experiment hadoop as a skunkworks in a small cluster (1-10 nodes) - Google Pro
- 如何在Visual Studio的工程中共享代码 l How do you share code between projects/solutions in Visual Studio
- From a response document, how do you update a field in the parent document?
- How do you remove the duplicate characters in a given string without using any additional buffer.
- How do you save a game in Unity iPhone?
- How do you make an object in C? Used in RTOS.
- 如何在Visual Studio的工程中共享代码 l How do you share code between projects/solutions in Visual Studio
- How do I define preprocessor macros in the xcode project settings
- What is Logical Volume Management and How Do You Enable It in Ubuntu?