广工EDA电平转脉冲实验代码（verilog HDL设计代码）

模块代码

// change.v
module change(clk,rst,ina,dataout);
input clk,rst,ina;
output dataout;
reg dataout;
parameter s0=2'b00,s1=2'b01,s2=2'b11;
reg[1:0] current_state,next_state;

always@(current_state or ina)
begin
case(current_state)
s0:begin
if(ina==1)
next_state<=s1;
else
next_state<=s0;
end
s1:begin
if(ina==1)
next_state<=s2;
else
next_state<=s0;
end
s2:begin
if(ina==1)
next_state<=s2;
else
next_state<=s0;
end
default:next_state<=s0;
endcase
end

always@(posedge clk or negedge rst)
if(!rst)
current_state<=s0;
else
current_state<=next_state;

always@(current_state)
dataout=(current_state==s1);
endmodule

测试代码

// test.v
`timescale 1ns/1ns
module testbench;
reg clk,rst;
reg ina;
wire dataout;
change test(clk,rst,ina,dataout);
always#(5) clk=~clk;
initial
begin
clk=0;
rst=0;
#5 rst=1;
end

initial
begin
ina=0;
#5; ina=1;
#50 ina=1;
#50 ina=0;
#50 ina=0;
#50 ina=1;
#50 ina=0;
#50 ina=1;
#50 ina=1;
#50 ina=1;
#50 ina=0;
#50 ina=1;
#50 ina=1;
end
initial
#1000 $finish;
endmodule