cpu之pc_reg

module pc_reg(
input wire clk,
input wire rst,
input wire stall_id,
input wire jump,
input wire[1:0] stall_branch_t,
input wire[31:0] pc1,
input wire[31:0] pc2,//专门为跳转指令设置的
output reg[31:0] pc
);

always @(posedge clk) begin
if (rst==1'b1) begin
pc=32'h0;

end else begin
if (jump!=1'b1) begin
if (stall_id==1'b0) begin
if (stall_branch_t==2'b10) begin
pc <= pc1-32'h4;
end else begin
pc<=pc1;
end
end else begin
pc <= pc1-32'h4;
end

end else begin
pc <= pc2;
end

end

end

endmodule