ISim P.20131013 (signature 0x7708f090)

ISim P.20131013 (signature 0x7708f090)

This is a Full version of ISim.

WARNING: File "F:/workspace/FPGA/xilinx/DDR3/tsb.v" Line 35. For instance tsb/uut/, width 12 of formal port sys_addr is not equal to width 16 of actual variable sys_addr.

WARNING: File "F:/workspace/FPGA/xilinx/DDR3/tsb.v" Line 41. For instance tsb/uut/, width 14 of formal port mcb5_dram_a is not equal to width 13 of actual signal mcb5_dram_a.

WARNING: File "F:/workspace/FPGA/xilinx/DDR3/tsb.v" Line 53. For instance tsb/uut/, width 14 of formal port mcb1_dram_a is not equal to width 13 of actual signal mcb1_dram_a.

Time resolution is 1 ps

Simulator is doing circuit initialization process.

ERROR: In process DDR_WR_FSM.vCont_96_11

FATAL ERROR:ISim: This application has discovered an exceptional condition from which it cannot recover. Process will terminate. To search for possible resolutions to this issue, refer to the Xilinx answer database by going to http://www.xilinx.com/support/answers/index.htm and search with keywords 'ISim' and 'FATAL ERROR'. For technical support on this issue, please open a WebCase with this project attached at http://www.xilinx.com/support.
INFO: Simulator is stopped.

ISim>

解决方案
Solution 1

This error can occur if there were syntax errors or problems while running the simulator executable. For more details, review the ISim log (isim.log) available in the project directory (or working directory, if launching simulation in batch mode).

This issue is currently under investigation to better address this condition in a future release of the ISE Simulator.

If the information contained in the log file does not help you address the problem, open a WebCase with Xilinx Technical Support for further assistance: http://www.xilinx.com/support/clearexpress/websupport.htm
Solution 2

This error can also occur if the simulator engine cannot allocate sufficient memory during elaboration of a large design. This is particularly applicable to Post-Route simulations due to the large structural netlist and timing back-annotation. Additionally,
this issue occurs mostly on Windows 32-bit machines as the 32-bit kernel can only allocate 2 GB per process; refer to (Xilinx Answer 14932).

To resolve this issue:

Run the simulation on a Linux 32-bit system; as the Linux 32-bit kernel can allocate up to 4 GB of memory.

Run the simulation on a supported 64-bit system. For a list of supported 64-bit simulators, refer to http://www.xilinx.com/ise/ossupport/.
Follow the instructions in (Xilinx Answer 14932) to enable 3 GB application support (Windows XP only).

This issue is currently under investigation to better address this condition in a future release of the ISE Simulator.

原因是直接跑Simulation但是存在综合语法问题，只要跑一遍Implementation就可以找到错误了