verilog testbench编写笔记

1、initial模块赋值时注意在时钟上升沿打入数据

initial 

begin

          ax = 16'd0;

          ay = 11'd0;
  bx = 16'd0;
  by = 11'd0; 
  enb1 = 1'b0;  
  enb2 = 1'b0;  
  enb3 = 1'b0;
  accum = 1'b0;
  loadconst = 1'b0;

#110;

@(posedge clk1)

          ax = 16'd2;

          ay = 11'd3;
  bx = 16'd3;
  by = 11'd2;
  enb1 = 1'b1;  
  enb2 = 1'b1;  
  enb3 = 1'b1;
  accum = 1'b1;
  loadconst = 1'b0;
 

end