【iCore4 双核心板_FPGA】例程十五：基于单口RAM的ARM+FPGA数据存取实验

int main(void)
{

/* USER CODE BEGIN 1 */
int i;
int address,data;
char error_flag = 0;
char receive_data[50];
char buffer[8];
char *p;
/* USER CODE END 1 */

/* MCU Configuration----------------------------------------------------------*/

/* Reset of all peripherals, Initializes the Flash interface and the Systick. */
HAL_Init();

/* USER CODE BEGIN Init */

/* USER CODE END Init */

/* Configure the system clock */
SystemClock_Config();

/* USER CODE BEGIN SysInit */

/* USER CODE END SysInit */

/* Initialize all configured peripherals */
MX_GPIO_Init();
MX_USART6_UART_Init();
MX_FMC_Init();

/* USER CODE BEGIN 2 */
usart6.initialize(115200);
usart6.printf("Hello, I am iCore4!\r\n");

/* USER CODE END 2 */

/* Infinite loop */
/* USER CODE BEGIN WHILE */
while (1)
{
/* USER CODE END WHILE */

/* USER CODE BEGIN 3 */
if(usart6.receive_ok_flag == 1){
usart6.receive_ok_flag = 0;
memset(receive_data,0,sizeof(receive_data));
memset(buffer,0,sizeof(buffer));
for(i = 0;i < 30;i ++){
receive_data[i] = usart6.receive_buffer[i];
}
p = receive_data;
i = 0;
while(*p != ':'){                                    //»ñÈ¡²Ù×÷ÃüÁwrite or read£©
buffer[i++] = *p++;
if(i > sizeof(buffer))i = 0;
}
for(i = 0;i < sizeof(buffer);i++){//½«ÃüÁîת»¯ÎªÐ¡Ð´×Ö·û
buffer[i] = tolower(buffer[i]);
}
if(memcmp(buffer,"write",strlen("write")) == 0){//Ö´ÐÐд²Ù×÷
error_flag = 0;
p++;
address = atoi(p);
if(address > 255)error_flag = 1;
p++;
p = strchr(p,',');
if(p == NULL)error_flag = 1;
if(!error_flag){
p++;
data = atoi(p);
if(data > 65535)error_flag = 1;

if(!error_flag){
fpga_write(address,data);
usart6.printf("Write FPGA Ram Successfully!");
}
}
}else{
if(memcmp(buffer,"read",strlen("read")) == 0){//Ö´ÐжÁ²Ù×÷
error_flag = 0;
p++;
address = atoi(p);
if(address > 255)error_flag = 1;
p++;
if(strchr(p,','))error_flag = 1;
if(!error_flag){
data = fpga_read(address);
usart6.printf("Read FPGA Ram:%d\r\n",data);
}
}else{
error_flag = 1;
}
}
if(error_flag){
LED_RED_ON;
LED_GREEN_OFF;
usart6.printf("Bad Command!\r\n");
}else{
LED_RED_OFF;
LED_GREEN_ON;
}
}
}
/* USER CODE END 3 */

}

module ram_ctrl(
input clk_100m,
input rst_n,
input wr_n,
input rd_n,
input cs0,
input [23:16]ab,
inout [15:0]db,
output led_red,
output led_green,
output led_blue
);
//----------------------------clk------------------------------//
wire wr,rd;
wire [15:0]data_out;

assign wr = wr_n | cs0;
assign rd = rd_n | cs0;

reg wr_0,wr_1;
always@(posedge clk_100m or negedge rst_n)
if(!rst_n)
begin
wr_0 <= 1'd1;
wr_1 <= 1'd1;
end
else
{wr_1,wr_0} <= {wr_0,wr};

wire clk = !wr_1 | !rd;
assign db = !rd ? data_out:16'hzzzz;

//----------------------------ram------------------------------//
ram u1(
.clock(clk),
.wren(!wr),
.rden(!rd),
.address(ab),
.data(db),
.q(data_out)
);

//----------------------------led_ctrl-------------------------//
reg led;
always@(posedge clk or negedge rst_n)
if(!rst_n)
led <= 1'd1;
else
led <= ~led;

assign {led_red,led_green,led_blue} = {1'd1,led,1'd1};

endmodule