FPGA之verilog第一天学习（00011101序列产生器）

module serilize_gen(
input i_sys_clk,
output data_out

);

//产生复位；

reg [3:0] rst_cnt = 4'd0;

always@(posedge i_sys_clk)begin
if(rst_cnt == 4'd10)begin
rst_cnt <= 4'd10;
end
else begin
rst_cnt <= rst_cnt;
end

end

wire rstn;

assign rstn = (rst_cnt == 4'd10);

//00011101序列循环产生

reg [2:0]cnt;

always@(posedge i_sys_clk or negedge rstn)begin
if(rstn==1'b0)begin
cnt <= 3'd0;
end
else if(cnt == 3'd7)begin

  cnt <= 3'd0;
end
else begin
cnt <= cnt + 1'b1;
end

end

reg seril_data;

always@(posedge i_sys_clk or negedge rstn)begin
if(rstn)begin
seril_data <= 1'b0;
end
else begin
case(cnt)
3'd0:begin
seril_data <= 1'b0;
end
3'd1:begin
seril_data <= 1'b0;
end
3'2:begin
seril_data <= 1'b0;
end
3'd3:begin
seril_data <= 1'b1;
end
3'd4:begin
seril_data <= 1'b1;
end
3'd5:begin
seril_data <= 1'b1;
end
3'd6:begin
seril_data <= 1'b0;
end
3'd7:begin
seril_data <= 1'b1;
end
endcase
end

end

assign data_out = seril_data;

endmodule