Zedboard---实验四驱动7段数码管

Zedboard—实验四驱动7段数码管

硬件准备

本节实验是使用开关输入，7段数码管显示。Digilent公司提供两位的7段数码管Pmod模块。与Zedboard连接图如下所示：



Digilent公司卖的pmod模块实在是太贵了，想不明白就两个数码管外加一个非门芯片和电阻电容能到￥108。



自己动手丰衣足食：两个7段数码管、一片74HC04、7个500欧姆电阻、排针。



这里注意：选择数字芯片应该满足Zedboard Pmod接口的电压供电（3.3V），电平相互兼容。74HC04的数据手册。

端口

两位的数码管控制：1. 七个管脚控制每个数码管的七段显示；2. 一个管脚控制选中两个数码管中的哪一个。为了视觉上感受到了两个数码管同时亮，两个数码管的选通速度要快于视觉残留的时间。首先，显示一个数码管。添加输出管脚：7位总线，这里叫做ssd，和一位输出控制数码管选通，它与数码管的阴极相连，即，ssdcat。模块的申明如下：

`timescale 1ns/1ns
module top (
input clk,
input [7:0] switch,
output reg [7:0] led,
output reg [6:0] ssd,
output reg ssdcat
);

数码管原理

每个数码管都有7个LED，标记为A到G：



为了显示数字，如下方式点亮LED值：



将数字显示对应为点亮LED的7位二进制值，如下表：

Input	Segments lit	Output value
0	ABCDEF	7’b1111110
1	BC	7’b0110000
2	ABDEG	7’b1101101
3	ABCDG	7’b1111001
4	BCFG	7’b0110011
5	ACDFG	7’b1011011
6	ACDEFG	7’b1011111
7	ABC	7’b1110000
8	ABCCDEFG	7’b1111111
9	ABCFG	7’b1110011
A	ABCEFG	7’b1110111
b	CDEFG	7’b0011111
C	ADEF	7’b1001110
d	BCDEG	7’b0111101
E	ADEFG	7’b1001111
F	AEFG	7’b1000111

使用第四位开关输入来控制数码管显示，这里采用Verilog语句中的case结构执行上表：

always @(posedge clk)
case (switch[3:0])
0: ssd <= 7'b1111110;
1: ssd <= 7'b0110000;
2: ssd <= 7'b1101101;
3: ssd <= 7'b1111001;
4: ssd <= 7'b0110011;
5: ssd <= 7'b1011011;
6: ssd <= 7'b1011111;
7: ssd <= 7'b1110000;
8: ssd <= 7'b1111111;
9: ssd <= 7'b1110011;
10: ssd <= 7'b1110111;
11: ssd <= 7'b0011111;
12: ssd <= 7'b1001110;
13: ssd <= 7'b0111101;
14: ssd <= 7'b1001111;
15: ssd <= 7'b1000111;
endcase

同时将管脚ssdcat输出置零：

always @(*) ssdcat = 0;

约束

这里选择Zedboard上的JA1和JB1 Pmod接口，将PmodSSD插入FPGA的bank13，将这些管脚约束为3.3V IO。

set_property IOSTANDARD LVCMOS33 [get_ports ssd]
set_property IOSTANDARD LVCMOS33 [get_ports ssdcat]

确定Zedboard管脚分配，下图为数码管与Zedboard的连接图，由此完成管脚分配：

set_property PACKAGE_PIN Y11 [get_ports {ssd[6]}]
set_property PACKAGE_PIN AA11 [get_ports {ssd[5]}]
set_property PACKAGE_PIN Y10 [get_ports {ssd[4]}]
set_property PACKAGE_PIN AA9 [get_ports {ssd[3]}]
set_property PACKAGE_PIN W12 [get_ports {ssd[2]}]
set_property PACKAGE_PIN W11 [get_ports {ssd[1]}]
set_property PACKAGE_PIN V10 [get_ports {ssd[0]}]
set_property PACKAGE_PIN W8 [get_ports ssdcat]

运行效果

代码文件

top.v：

`timescale 1ns / 1ns
module top
(
input clk,
input [7:0] switch,
output reg [7:0] led,
output reg [6:0] ssd,
output reg ssdcat
);

always @(posedge clk) led <= switch;

always @(posedge clk)
case (switch[3:0])
0: ssd <= 7'b1111110;
1: ssd <= 7'b0110000;
2: ssd <= 7'b1101101;
3: ssd <= 7'b1111001;
4: ssd <= 7'b0110011;
5: ssd <= 7'b1011011;
6: ssd <= 7'b1011111;
7: ssd <= 7'b1110000;
8: ssd <= 7'b1111111;
9: ssd <= 7'b1110011;
10: ssd <= 7'b1110111;
11: ssd <= 7'b0011111;
12: ssd <= 7'b1001110;
13: ssd <= 7'b0111101;
14: ssd <= 7'b1001111;
15: ssd <= 7'b1000111;
endcase

always @(*) ssdcat = 0;

endmodule

top.xdc

set_property IOSTANDARD LVCMOS33 [get_ports clk]
set_property PACKAGE_PIN Y9 [get_ports clk]
create_clock -period 10 [get_ports clk]

set_property IOSTANDARD LVCMOS33 [get_ports led]
set_property IOSTANDARD LVCMOS25 [get_ports switch]
set_property PACKAGE_PIN T22 [get_ports {led[0]}]
set_property PACKAGE_PIN T21 [get_ports {led[1]}]
set_property PACKAGE_PIN U22 [get_ports {led[2]}]
set_property PACKAGE_PIN U21 [get_ports {led[3]}]
set_property PACKAGE_PIN V22 [get_ports {led[4]}]
set_property PACKAGE_PIN W22 [get_ports {led[5]}]
set_property PACKAGE_PIN U19 [get_ports {led[6]}]
set_property PACKAGE_PIN U14 [get_ports {led[7]}]
set_property PACKAGE_PIN F22 [get_ports {switch[0]}]
set_property PACKAGE_PIN G22 [get_ports {switch[1]}]
set_property PACKAGE_PIN H22 [get_ports {switch[2]}]
set_property PACKAGE_PIN F21 [get_ports {switch[3]}]
set_property PACKAGE_PIN H19 [get_ports {switch[4]}]
set_property PACKAGE_PIN H18 [get_ports {switch[5]}]
set_property PACKAGE_PIN H17 [get_ports {switch[6]}]
set_property PACKAGE_PIN M15 [get_ports {switch[7]}]

set_property IOSTANDARD LVCMOS33 [get_ports ssd]
set_property IOSTANDARD LVCMOS33 [get_ports ssdcat]
set_property PACKAGE_PIN Y11 [get_ports {ssd[6]}]
set_property PACKAGE_PIN AA11 [get_ports {ssd[5]}]
set_property PACKAGE_PIN Y10 [get_ports {ssd[4]}]
set_property PACKAGE_PIN AA9 [get_ports {ssd[3]}]
set_property PACKAGE_PIN W12 [get_ports {ssd[2]}]
set_property PACKAGE_PIN W11 [get_ports {ssd[1]}]
set_property PACKAGE_PIN V10 [get_ports {ssd[0]}]
set_property PACKAGE_PIN W8 [get_ports ssdcat]

原文连接