DSP48E1的使用，实现RGB转YUV空间（2）---一步一步做图像拼接
2017-02-10 20:44
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DSP48E1的使用，实现RGB转YUV空间（2）---一步一步做图像拼接
0赞发表于 2014/11/6 18:06:15 阅读（1543） 评论（0）
这是接着上一篇文章，上一面文章主要介绍了下引脚以及应用的背景，这篇我主要是把源码贴出来，在程序中看看DSP24E1的各个属性是如何设置的。
先看一下源码
//-----------------Y的系数计算-----------------------------------
DSP48E1 #(
// Feature Control Attributes: Data Path Selection
.A_INPUT("DIRECT"), // Selects A input source, "DIRECT" (A port) or "CASCADE" (ACIN port)
.B_INPUT("DIRECT"), // Selects B input source, "DIRECT" (B port) or "CASCADE" (BCIN port)
.USE_DPORT("FALSE"), // Select D port usage (TRUE or FALSE)，没有使用预加器，D端口
.USE_MULT("MULTIPLY"), // Select multiplier usage ("MULTIPLY", "DYNAMIC", or "NONE")，使用了乘法，
// Pattern Detector Attributes: Pattern Detection Configuration
.AUTORESET_PATDET("NO_RESET"), // "NO_RESET", "RESET_MATCH", "RESET_NOT_MATCH"，RESET P 寄存器
.MASK(48'h3fffffffffff), // 48-bit mask value for pattern detect (1=ignore)
.PATTERN(48'h000000000000), // 48-bit pattern match for pattern detect
.SEL_MASK("MASK"), // "C", "MASK", "ROUNDING_MODE1", "ROUNDING_MODE2"
.SEL_PATTERN("PATTERN"), // Select pattern value ("PATTERN" or "C")
.USE_PATTERN_DETECT("NO_PATDET"), // Enable pattern detect ("PATDET" or "NO_PATDET")
// Register Control Attributes: Pipeline Register Configuration
.ACASCREG(0), // Number of pipeline stages between A/ACIN and ACOUT (0, 1 or 2)
.ADREG(0), // Number of pipeline stages for pre-adder (0 or 1)
.ALUMODEREG(1), // Number of pipeline stages for ALUMODE (0 or 1)
.AREG(0), // Number of pipeline stages for A (0, 1 or 2)
.BCASCREG(0), // Number of pipeline stages between B/BCIN and BCOUT (0, 1 or 2)
.BREG(0), // Number of pipeline stages for B (0, 1 or 2)
.CARRYINREG(1), // Number of pipeline stages for CARRYIN (0 or 1)
.CARRYINSELREG(1), // Number of pipeline stages for CARRYINSEL (0 or 1)
.CREG(0)
13a8e
, // Number of pipeline stages for C (0 or 1)
.DREG(0), // Number of pipeline stages for D (0 or 1)
.INMODEREG(1), // Number of pipeline stages for INMODE (0 or 1)
.MREG(1), // Number of multiplier pipeline stages (0 or 1)
.OPMODEREG(1), // Number of pipeline stages for OPMODE (0 or 1)
.PREG(1), // Number of pipeline stages for P (0 or 1)
.USE_SIMD("ONE48") // SIMD selection ("ONE48", "TWO24", "FOUR12")
)
mult_r1 (
// Cascade: 30-bit (each) output: Cascade Ports
.ACOUT(), // 30-bit output: A port cascade output
.BCOUT(), // 18-bit output: B port cascade output
.CARRYCASCOUT(), // 1-bit output: Cascade carry output
.MULTSIGNOUT(), // 1-bit output: Multiplier sign cascade output
.PCOUT(pc_r1), // 48-bit output: Cascade output
// Control: 1-bit (each) output: Control Inputs/Status Bits
.OVERFLOW(), // 1-bit output: Overflow in add/acc output
.PATTERNBDETECT(), // 1-bit output: Pattern bar detect output
.PATTERNDETECT(), // 1-bit output: Pattern detect output
.UNDERFLOW(), // 1-bit output: Underflow in add/acc output
// Data: 4-bit (each) output: Data Ports
.CARRYOUT(), // 4-bit output: Carry output
.P(), // 48-bit output: Primary data output
// Cascade: 30-bit (each) input: Cascade Ports
.ACIN(0), // 30-bit input: A cascade data input
.BCIN(0), // 18-bit input: B cascade input
.CARRYCASCIN(0), // 1-bit input: Cascade carry input
.MULTSIGNIN(0), // 1-bit input: Multiplier sign input
.PCIN(), // 48-bit input: P cascade input
// Control: 4-bit (each) input: Control Inputs/Status Bits
.ALUMODE(0000), // 4-bit input: ALU control input,输出为Z+X+Y+CIN
.CARRYINSEL(000), // 3-bit input: Carry select input, general interconnect
.CEINMODE(1), // 1-bit input: Clock enable input for INMODEREG
.CLK(clk), // 1-bit input: Clock input
.INMODE(00000), // 5-bit input: INMODE control input
.OPMODE(0110101), // 7-bit input: Operation mode input
.RSTINMODE(0), // 1-bit input: Reset input for INMODEREG
// Data: 30-bit (each) input: Data Ports
.A(a_r1), // 30-bit input: A data input
.B(b_r1), // 18-bit input: B data input
.C(c1), // 48-bit input: C data input
.CARRYIN(0), // 1-bit input: Carry input signal
.D(0), // 25-bit input: D data input
// Reset/Clock Enable:Reset/Clock Enable Inputs，没有使用流水线，所以对应路径上的时钟使能都为0
.CEA1(0), // 1-bit input: Clock enable input for 1st stage AREG
.CEA2(0), // 1-bit input: Clock enable input for 2nd stage AREG
.CEAD(0), // 1-bit input: Clock enable input for ADREG
.CEALUMODE(1), // 1-bit input: Clock enable input for ALUMODERE，使能二级运算电路模式选择时钟
.CEB1(0), // 1-bit input: Clock enable input for 1st stage BREG
.CEB2(0), // 1-bit input: Clock enable input for 2nd stage BREG
.CEC(0), // 1-bit input: Clock enable input for CREG
.CECARRYIN(1), // 1-bit input: Clock enable input for CARRYINREG
.CECTRL(1), // 1-bit input: Clock enable input for OPMODEREG and CARRYINSELREG
.CED(0), // 1-bit input: Clock enable input for DREG
.CEM(1), // 1-bit input: Clock enable input for MREG
.CEP(1), // 1-bit input: Clock enable input for PREG
.RSTA(0), // 1-bit input:RSTA/B/C/D都置成0，默认为1，默认状态为复位状态
.RSTALLCARRYIN(0), // 1-bit input: Reset input for CARRYINREG
.RSTALUMODE(0), // 1-bit input: Reset input for ALUMODEREG
.RSTB(0),
.RSTC(0),
.RSTCTRL(0), // 1-bit input: 复位OPMODEREG and CARRYINSELREG，置成0，默认为1；
.RSTD(0),
.RSTM(0), // 1-bit input: Reset input for MREG
.RSTP(0) // 1-bit input: Reset input for PREG
);
DSP48E1 #(
// Feature Control Attributes: Data Path Selection
.A_INPUT("DIRECT"), // Selects A input source, "DIRECT" (A port) or "CASCADE" (ACIN port)
.B_INPUT("DIRECT"), // Selects B input source, "DIRECT" (B port) or "CASCADE" (BCIN port)
.USE_DPORT("FALSE"), // Select D port usage (TRUE or FALSE)，没有使用预加器，D端口
.USE_MULT("MULTIPLY"), // Select multiplier usage ("MULTIPLY", "DYNAMIC", or "NONE")，使用了乘法，
// Pattern Detector Attributes: Pattern Detection Configuration
.AUTORESET_PATDET("NO_RESET"), // "NO_RESET", "RESET_MATCH", "RESET_NOT_MATCH"，RESET P 寄存器
.MASK(48'h3fffffffffff), // 48-bit mask value for pattern detect (1=ignore)
.PATTERN(48'h000000000000), // 48-bit pattern match for pattern detect
.SEL_MASK("MASK"), // "C", "MASK", "ROUNDING_MODE1", "ROUNDING_MODE2"
.SEL_PATTERN("PATTERN"), // Select pattern value ("PATTERN" or "C")
.USE_PATTERN_DETECT("NO_PATDET"), // Enable pattern detect ("PATDET" or "NO_PATDET")
// Register Control Attributes: Pipeline Register Configuration
.ACASCREG(0), // Number of pipeline stages between A/ACIN and ACOUT (0, 1 or 2)
.ADREG(0), // Number of pipeline stages for pre-adder (0 or 1)
.ALUMODEREG(1), // Number of pipeline stages for ALUMODE (0 or 1)
.AREG(0), // Number of pipeline stages for A (0, 1 or 2)
.BCASCREG(0), // Number of pipeline stages between B/BCIN and BCOUT (0, 1 or 2)
.BREG(0), // Number of pipeline stages for B (0, 1 or 2)
.CARRYINREG(1), // Number of pipeline stages for CARRYIN (0 or 1)
.CARRYINSELREG(1), // Number of pipeline stages for CARRYINSEL (0 or 1)
.CREG(0), // Number of pipeline stages for C (0 or 1)
.DREG(0), // Number of pipeline stages for D (0 or 1)
.INMODEREG(1), // Number of pipeline stages for INMODE (0 or 1)
.MREG(1), // Number of multiplier pipeline stages (0 or 1)
.OPMODEREG(1), // Number of pipeline stages for OPMODE (0 or 1)
.PREG(1), // Number of pipeline stages for P (0 or 1)
.USE_SIMD("ONE48") // SIMD selection ("ONE48", "TWO24", "FOUR12")
)
mult_g1 (
// Cascade: 30-bit (each) output: Cascade Ports
.ACOUT(), // 30-bit output: A port cascade output
.BCOUT(), // 18-bit output: B port cascade output
.CARRYCASCOUT(), // 1-bit output: Cascade carry output
.MULTSIGNOUT(), // 1-bit output: Multiplier sign cascade output
.PCOUT(pc_g1), // 48-bit output: Cascade output
// Control: 1-bit (each) output: Control Inputs/Status Bits
.OVERFLOW(), // 1-bit output: Overflow in add/acc output
.PATTERNBDETECT(), // 1-bit output: Pattern bar detect output
.PATTERNDETECT(), // 1-bit output: Pattern detect output
.UNDERFLOW(), // 1-bit output: Underflow in add/acc output
// Data: 4-bit (each) output: Data Ports
.CARRYOUT(), // 4-bit output: Carry output
.P(), // 48-bit output: Primary data output
// Cascade: 30-bit (each) input: Cascade Ports
.ACIN(0), // 30-bit input: A cascade data input
.BCIN(0), // 18-bit input: B cascade input
.CARRYCASCIN(0), // 1-bit input: Cascade carry input
.MULTSIGNIN(0), // 1-bit input: Multiplier sign input
.PCIN(pc_r1), // 48-bit input: P cascade input
// Control: 4-bit (each) input: Control Inputs/Status Bits
.ALUMODE(0000), // 4-bit input: ALU control input,输出为Z+X+Y+CIN
.CARRYINSEL(000), // 3-bit input: Carry select input, general interconnect
.CEINMODE(1), // 1-bit input: Clock enable input for INMODEREG
.CLK(clk), // 1-bit input: Clock input
.INMODE(00000), // 5-bit input: INMODE control input
.OPMODE(0010101), // 7-bit input: Operation mode input
.RSTINMODE(0), // 1-bit input: Reset input for INMODEREG
// Data: 30-bit (each) input: Data Ports
.A(a_g1), // 30-bit input: A data input
.B(b_g1), // 18-bit input: B data input
.C(0), // 48-bit input: C data input
.CARRYIN(0), // 1-bit input: Carry input signal
.D(0), // 25-bit input: D data input
// Reset/Clock Enable:Reset/Clock Enable Inputs，没有使用流水线，所以对应路径上的时钟使能都为0
.CEA1(0), // 1-bit input: Clock enable input for 1st stage AREG
.CEA2(0), // 1-bit input: Clock enable input for 2nd stage AREG
.CEAD(0), // 1-bit input: Clock enable input for ADREG
.CEALUMODE(1), // 1-bit input: Clock enable input for ALUMODERE，使能二级运算电路模式选择时钟
.CEB1(0), // 1-bit input: Clock enable input for 1st stage BREG
.CEB2(0), // 1-bit input: Clock enable input for 2nd stage BREG
.CEC(0), // 1-bit input: Clock enable input for CREG
.CECARRYIN(1), // 1-bit input: Clock enable input for CARRYINREG
.CECTRL(1), // 1-bit input: Clock enable input for OPMODEREG and CARRYINSELREG
.CED(0), // 1-bit input: Clock enable input for DREG
.CEM(1), // 1-bit input: Clock enable input for MREG
.CEP(1), // 1-bit input: Clock enable input for PREG
.RSTA(0), // 1-bit input:RSTA/B/C/D都置成0，默认为1，默认状态为复位状态
.RSTALLCARRYIN(0), // 1-bit input: Reset input for CARRYINREG
.RSTALUMODE(0), // 1-bit input: Reset input for ALUMODEREG
.RSTB(0),
.RSTC(0),
.RSTCTRL(0), // 1-bit input: 复位OPMODEREG and CARRYINSELREG，置成0，默认为1；
.RSTD(0),
.RSTM(0), // 1-bit input: Reset input for MREG
.RSTP(0) // 1-bit input: Reset input for PREG
);
DSP48E1 #(
// Feature Control Attributes: Data Path Selection
.A_INPUT("DIRECT"), // Selects A input source, "DIRECT" (A port) or "CASCADE" (ACIN port)
.B_INPUT("DIRECT"), // Selects B input source, "DIRECT" (B port) or "CASCADE" (BCIN port)
.USE_DPORT("FALSE"), // Select D port usage (TRUE or FALSE)，没有使用预加器，D端口
.USE_MULT("MULTIPLY"), // Select multiplier usage ("MULTIPLY", "DYNAMIC", or "NONE")，使用了乘法，
// Pattern Detector Attributes: Pattern Detection Configuration
.AUTORESET_PATDET("NO_RESET"), // "NO_RESET", "RESET_MATCH", "RESET_NOT_MATCH"，RESET P 寄存器
.MASK(48'h3fffffffffff), // 48-bit mask value for pattern detect (1=ignore)
.PATTERN(48'h000000000000), // 48-bit pattern match for pattern detect
.SEL_MASK("MASK"), // "C", "MASK", "ROUNDING_MODE1", "ROUNDING_MODE2"
.SEL_PATTERN("PATTERN"), // Select pattern value ("PATTERN" or "C")
.USE_PATTERN_DETECT("NO_PATDET"), // Enable pattern detect ("PATDET" or "NO_PATDET")
// Register Control Attributes: Pipeline Register Configuration
.ACASCREG(0), // Number of pipeline stages between A/ACIN and ACOUT (0, 1 or 2)
.ADREG(0), // Number of pipeline stages for pre-adder (0 or 1)
.ALUMODEREG(1), // Number of pipeline stages for ALUMODE (0 or 1)
.AREG(0), // Number of pipeline stages for A (0, 1 or 2)
.BCASCREG(0), // Number of pipeline stages between B/BCIN and BCOUT (0, 1 or 2)
.BREG(0), // Number of pipeline stages for B (0, 1 or 2)
.CARRYINREG(1), // Number of pipeline stages for CARRYIN (0 or 1)
.CARRYINSELREG(1), // Number of pipeline stages for CARRYINSEL (0 or 1)
.CREG(0), // Number of pipeline stages for C (0 or 1)
.DREG(0), // Number of pipeline stages for D (0 or 1)
.INMODEREG(1), // Number of pipeline stages for INMODE (0 or 1)
.MREG(1), // Number of multiplier pipeline stages (0 or 1)
.OPMODEREG(1), // Number of pipeline stages for OPMODE (0 or 1)
.PREG(1), // Number of pipeline stages for P (0 or 1)
.USE_SIMD("ONE48") // SIMD selection ("ONE48", "TWO24", "FOUR12")
)
mult_b1 (
// Cascade: 30-bit (each) output: Cascade Ports
.ACOUT(), // 30-bit output: A port cascade output
.BCOUT(), // 18-bit output: B port cascade output
.CARRYCASCOUT(), // 1-bit output: Cascade carry output
.MULTSIGNOUT(), // 1-bit output: Multiplier sign cascade output
.PCOUT(pc_g1), // 48-bit output: Cascade output
// Control: 1-bit (each) output: Control Inputs/Status Bits
.OVERFLOW(), // 1-bit output: Overflow in add/acc output
.PATTERNBDETECT(), // 1-bit output: Pattern bar detect output
.PATTERNDETECT(), // 1-bit output: Pattern detect output
.UNDERFLOW(), // 1-bit output: Underflow in add/acc output
// Data: 4-bit (each) output: Data Ports
.CARRYOUT(), // 4-bit output: Carry output
.P(p_b1), // 48-bit output: Primary data output
// Cascade: 30-bit (each) input: Cascade Ports
.ACIN(0), // 30-bit input: A cascade data input
.BCIN(0), // 18-bit input: B cascade input
.CARRYCASCIN(0), // 1-bit input: Cascade carry input
.MULTSIGNIN(0), // 1-bit input: Multiplier sign input
.PCIN(pc_g1), // 48-bit input: P cascade input
// Control: 4-bit (each) input: Control Inputs/Status Bits
.ALUMODE(0000), // 4-bit input: ALU control input,输出为Z+X+Y+CIN
.CARRYINSEL(000), // 3-bit input: Carry select input, general interconnect
.CEINMODE(1), // 1-bit input: Clock enable input for INMODEREG
.CLK(clk), // 1-bit input: Clock input
.INMODE(00000), // 5-bit input: INMODE control input
.OPMODE(0010101), // 7-bit input: Operation mode input
.RSTINMODE(0), // 1-bit input: Reset input for INMODEREG
// Data: 30-bit (each) input: Data Ports
.A(a_b1), // 30-bit input: A data input
.B(b_b1), // 18-bit input: B data input
.C(0), // 48-bit input: C data input
.CARRYIN(0), // 1-bit input: Carry input signal
.D(0), // 25-bit input: D data input
// Reset/Clock Enable:Reset/Clock Enable Inputs，没有使用流水线，所以对应路径上的时钟使能都为0
.CEA1(0), // 1-bit input: Clock enable input for 1st stage AREG
.CEA2(0), // 1-bit input: Clock enable input for 2nd stage AREG
.CEAD(0), // 1-bit input: Clock enable input for ADREG
.CEALUMODE(1), // 1-bit input: Clock enable input for ALUMODERE，使能二级运算电路模式选择时钟
.CEB1(0), // 1-bit input: Clock enable input for 1st stage BREG
.CEB2(0), // 1-bit input: Clock enable input for 2nd stage BREG
.CEC(0), // 1-bit input: Clock enable input for CREG
.CECARRYIN(1), // 1-bit input: Clock enable input for CARRYINREG
.CECTRL(1), // 1-bit input: Clock enable input for OPMODEREG and CARRYINSELREG
.CED(0), // 1-bit input: Clock enable input for DREG
.CEM(1), // 1-bit input: Clock enable input for MREG
.CEP(1), // 1-bit input: Clock enable input for PREG
.RSTA(0), // 1-bit input:RSTA/B/C/D都置成0，默认为1，默认状态为复位状态
.RSTALLCARRYIN(0), // 1-bit input: Reset input for CARRYINREG
.RSTALUMODE(0), // 1-bit input: Reset input for ALUMODEREG
.RSTB(0),
.RSTC(0),
.RSTCTRL(0), // 1-bit input: 复位OPMODEREG and CARRYINSELREG，置成0，默认为1；
.RSTD(0),
.RSTM(0), // 1-bit input: Reset input for MREG
.RSTP(0) // 1-bit input: Reset input for PREG
);
在讲解计算之前，我们先记R分量的系数A1，G分量的系数G1，B分量的系数B1，常数为C1；
三个DSP48e1的进行串联，第一个dsp48e1的
X=AxB，A是25位，B的是18位，X=R x A1，Y= R x A1，Z=C1；
第一个DSP48E1的输出是Pcout，输入至第二个DSP48E1的PCIN，
第二个DSP48E1的输入是X=G x G1，Y= G x G1，Z=PCIN；输出是Pcout，输入至第三个dsp48e1的Pcin
第三个DSP48E1的输入是X=B x B1, Y= BxB1,Z=Pcin, 输出是P，
三个DSP48e1形成级联，完成三次乘法运算，三次加法运算；
经过仿真，运算时间在4个时钟周期。
至于负数，我们怎么办呢？把负数转换成补码形式即可，即可以参与运算。
输出是48位数据；且输出的和是 2xR x A1+2xG x G1+2xB x B1=P[47:0]；
如何得到我们想要的数据呢？
是这样的，R/G/B分量在这个模块运算之前，左移了15位，A1，B1,G1系数与原始的转换系数相比，左移了17位，在加上系数2，这样一共扩大了33倍，即左移了33位；输出结果是48位，我们通过先左移，再右移，最后可以得到系数是P[40:33]，这样就得到了Y分量的系数。
运用dsp48e1，就要在位数上多做功夫。
DSP48E1还要其他强大的功能，这里没用使用到，最后还是把我的笔记贴过来，至于属性怎么设置，具体细节可能还是要查找手册的，这里三言两语是没有办法说清楚的。
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