很简单的例子，仅仅加时钟周期约束的条件下时序波形图分析

为什么建立时间的datarequiretime  会在lauch clock的后面 是因为launch clock到目的寄存器还有一段延迟

简单的例子，仅仅加时钟周期约束的条件下，

 

create_clock -period 10.000 -name clk_in [get_ports {clk_in}]

 

 

用TimeQuest分析仅会得到一路path的分析，reg1 to reg2，时序图如下：





clock arrival time=latch edge+clock network delay to destination register                                           

11.110=10+1.110

data required time =clock arrival time -u/tsu                                                                                   

11.125=11.110-(-0.015)

data arrival time=launch edge +clock network delay source register +u/tco+register-to-register delay  

1.438=0+1.148+0.199+0.091

clock setup slack =data required time -data arrival time                                                                   

9.687 = 11.125-1.438

 

set_input_delay -clock { clk_in } -add_delay 1.200 [get_ports {data_in}]

set_output_delay -clock { clk_in } -add_delay 2.000 [get_ports data_out]

重新运行TimeQuest，可以看到3个path分析

　　1) data_in to reg1





 



2) reg1 to reg2





 

[b]3) reg2 to data_out







 　可以看到，输入路径在data arrival time上加上了input delay；输出路径在data required time上减去了output delay;分别表现为对setup和hold时间的影响。