vhdl基础---分频

ibrary IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith;
use ieee.std_logic_unsigned;

entity test_1 is
generic (n: integer:=6);
port(
clkin: in std_logic;-----rate=n,n is odd;
clkout: out std_logic ---relative FPGA,clkout is out signal;
);
end test_1;

architecture Behavioral of test_1 is
signal cnt:integer range 0 to n-1;
begin
process (clkin)------count
begin
if (clkin'event and clkin='1') then
if(cnt<n-1) then
cnt<=cnt+1;
else
cnt<=0;
end if;
end if;
end process;

process(cnt) -----根据计数值，控制输出始终脉冲的高低电平
begin
if(cnt<n/2) then
clkout<='1';
else
clkout<='0';
end if;
end process;

end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith;
use ieee.std_logic_unsigned;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity test_1 is
generic (n: integer:=10);
port(
clkin: in std_logic;-----rate=n,n is odd;
clkout: out std_logic ---relative FPGA,clkout is out signal;
);
end test_1;

architecture Behavioral of test_1 is
signal cnt:integer range 0 to n/2-1;
signal temp :std_logic;
begin
process (clkin)------count
begin
if (clkin'event and clkin='1') then
if(cnt=n/2-1) then
cnt<=0;
temp<=not temp;
else
cnt<=cnt+1;
end if;
end if;
end process;

clkout<=temp;---clkout和temp都是信号，均可传出来

end Behavioral;

entity test_1 is
generic (n: integer:=5);
port(
clkin: in std_logic;-----rate=n,n is 偶数;
clkout: out std_logic ---relative FPGA,clkout is out signal;
);
end test_1;

architecture Behavioral of test_1 is
signal cnt1,cnt2:integer range 0 to n/2-1;

begin
process (clkin)------count
begin
if (clkin'event and clkin='1') then ------上升沿计数
if(cnt1<n-1) then
cnt1<=cnt1+1;

else
cnt1<=0;
end if;
end if;
end process;

process (clkin)------count
begin
if (clkin'event and clkin='0') then ------下升沿计数
if(cnt2<n-1) then
cnt2<=cnt2+1;

else
cnt2<=0;
end if;
end if;
end process;

clkout<='1' when cnt1<(n-1)/2 else
'0' when cnt2<(n-1)/2;

end Behavioral;

entity test_1 is----占空比3：:1 的偶数分频器
-----当计数值为0-2时，输出高电平，到计数值为
---3-9时，输出低电平
generic (
n: integer:=10;
m: integer:=3  ----占空比为m:n,rate=n;
);
port(
clkin: in std_logic;-----rate=n,n is 偶数;
clkout: out std_logic ---relative FPGA,clkout is out signal;
);
end test_1;

architecture Behavioral of test_1 is
signal cnt1:integer range 0 to n-1;

begin
process (clkin)------count
begin
if (clkin'event and clkin='1') then ------上升沿计数
if(cnt1<n-1) then
cnt1<=cnt1+1;

else
cnt1<=0;
end if;
end if;
end process;

clkout<='1' when cnt1<m else
'0' ;

end Behavioral;