Ethernet IP Core介绍

The Ethernet IP Core is a 10/100 Media Access Controller (MAC). It consists of a synthesizable Verilog RTL core that provides all features necessary
to implement the Layer 2 protocol of the Ethernet standard. It is designed to run according to the IEEE 802.3 and 802.3u specifications that define the 10 Mbps and 100 Mbps
Ethernet standards, respectively.

使用Verilog语言实现的10/100M MAC子层传输协议。是OSI中的数据链路层功能，完成与物理层数据交换。MAC是一个中间传输层，上层链接应用层，下层需要专门的PHY物理芯片实现与物理层管理。

下图是IP核整体框架图：



包含的功能包括：

(1)TX Ethernet MAC (transmit function) block with the CRC generator

(2) RX Ethernet MAC (receive function) block with the CRC generator

(3) MAC control block ,实现全双工流控制

(4) Management block (MIIM)，与外部PHY芯片接口与控制

(5) Host interface，与内部CPU相连，实现控制发起。

下图是IP程序模块调用图：



The module
eth_top.v consists of sub modules
eth_miim.v,
eth_registers.v,eth_maccontrol.v,
eth_txethmac.v eth_rxethmac.v,
eth_wishbone.v, eth_macstatus.v
and some logic for synchronizing, multiplexing and registeringoutputs.。

接下来将分模块介绍这些模块与功能仿真。

2015-11-17，晚。DOTA2游戏后。