【FPGA】FPGA错误汇总 ( 不断更新... )

1. 设计顶层测试文件时报错误！

Started : "Behavioral Check Syntax".
Determining files marked for global include in the design...
Running vlogcomp...
Command Line: vlogcomp -work isim_temp -intstyle ise -prj {E:/FPGA Projects/Test1/TestFig_stx_beh.prj}
Determining compilation order of HDL files
Analyzing Verilog file "E:/FPGA Projects/Test1/Source/Module1.v" into library isim_temp
ERROR:HDLCompiler:806 - "E:/FPGA Projects/Test1/Source/Module1.v" Line 1: Syntax error near " ".
WARNING:HDLCompiler:1591 - "E:/FPGA Projects/Test1/Source/Module1.v" Line 1: Root scope declaration is not allowed in verilog 95/2K mode
Verilog file E:/FPGA Projects/Test1/Source/Module1.v ignored due to errors

Process "Behavioral Check Syntax" failed

Process "Behavioral Check Syntax" failed

找了各种方法，查了各种语法，无果。。。
最后问题找到：语法没写错，公司电脑ISE软件加密问题！！！坑爹。。
果断弃之，在外部编辑器中写代码！

2. 报错：Signal count[24] in unit led1 is connected to following multiple drivers:
原因：在多个always块里对同一个reg型变量进行赋值；

3. 报错：Port connections cannot be mixed ordered and named
原因：语法问题，查找！ 比如实例化时 少了.