ALTERA DE2 之 verilog HDL 学习笔记01 程序的并行

最近刚开始学习verilog HDL语言，正好手上有从学长那里借到的一块ALTERA DE2 的FPGA开发板。趁着假期先学习学习。

由于有一些C语言基础，所以在看verilog HDL 语法时看得很快。它与C语言最大的不同就是，HDL语言有很多的module，并且这些module之间是并行的关系。但是在有些模块的内部就是顺序执行的，比如begin和always等。

下面通过一个简单的led闪烁的module来验证。程序有1个top-module 和 4个不同延时的sub-module。4个子module是并行执行。

led0_module.v

module led0_module
(
clk, rst_n, led_out
);

input clk;
input rst_n;
output led_out;

parameter T10MS = 25'd20_000_000;

reg [24:0] count;

always @(posedge clk or negedge rst_n)
if (!rst_n)
count <= 25'd0;
else if (count == T10MS)
count <= 25'd0;
else
count <= count + 1'b1;

reg rled_out;

always @(posedge clk or negedge rst_n)
if (!rst_n)
rled_out <= 1'b0;
else if (count >= 25'd0 && count < 25'd5_000_000)
rled_out <= 1'b1;
else
rled_out <= 1'b0;

assign led_out = rled_out;

endmodule

led1_module.v

//1bit led output when rst_n is pushed led_out =0
module led1_module
(
<span style="white-space:pre">	</span>clk,rst_n,led_out
);

<span style="white-space:pre">	</span>input clk;
<span style="white-space:pre">	</span>input rst_n;
<span style="white-space:pre">	</span>output led_out;
<span style="white-space:pre">	</span>
<span style="white-space:pre">	</span>parameter T10MS=25'd20000000;
<span style="white-space:pre">	</span>reg [24:0] count;
<span style="white-space:pre">	</span>
<span style="white-space:pre">	</span>always @(posedge clk or negedge rst_n)
<span style="white-space:pre">		</span>if(!rst_n)
<span style="white-space:pre">			</span>count<=25'd0;
<span style="white-space:pre">		</span>else if(count == T10MS)
<span style="white-space:pre">			</span>count<=25'd0;
<span style="white-space:pre">		</span>else 
<span style="white-space:pre">			</span>count<=count+1'b1;

<span style="white-space:pre">	</span>reg rled_out;
<span style="white-space:pre">	</span>
<span style="white-space:pre">	</span>always @(posedge clk or negedge rst_n)
<span style="white-space:pre">		</span>if(!rst_n)
<span style="white-space:pre">			</span>rled_out<=1'b0;
<span style="white-space:pre">		</span>else if(count >= 25'b0 && count < 25'd10000000)
<span style="white-space:pre">			</span>rled_out<=1'b1;
<span style="white-space:pre">		</span>else 
<span style="white-space:pre">			</span>rled_out<=1'b0;
<span style="white-space:pre">			</span>
<span style="white-space:pre">	</span>assign led_out = rled_out;
endmodule

led2_module.v

//1bit led output when rst_n is pushed led_out =0
module led2_module
(
<span style="white-space:pre">	</span>clk,rst_n,led_out
);

<span style="white-space:pre">	</span>input clk;
<span style="white-space:pre">	</span>input rst_n;
<span style="white-space:pre">	</span>output led_out;
<span style="white-space:pre">	</span>
<span style="white-space:pre">	</span>parameter T10MS=25'd20000000;
<span style="white-space:pre">	</span>reg [24:0] count;
<span style="white-space:pre">	</span>
<span style="white-space:pre">	</span>always @(posedge clk or negedge rst_n)
<span style="white-space:pre">	</span>if(!rst_n)
<span style="white-space:pre">		</span>count<=25'd0;
<span style="white-space:pre">	</span>else if(count == T10MS)
<span style="white-space:pre">		</span>count<=25'd0;
<span style="white-space:pre">	</span>else 
<span style="white-space:pre">		</span>count<=count+1'b1;

<span style="white-space:pre">	</span>reg rled_out;
<span style="white-space:pre">	</span>
<span style="white-space:pre">	</span>always @(posedge clk or negedge rst_n)
<span style="white-space:pre">		</span>if(!rst_n)
<span style="white-space:pre">			</span>rled_out<=1'b0;
<span style="white-space:pre">		</span>else if(count >= 25'b0 && count < 25'd15000000)
<span style="white-space:pre">			</span>rled_out<=1'b1;
<span style="white-space:pre">		</span>else 
<span style="white-space:pre">			</span>rled_out<=1'b0;
<span style="white-space:pre">			</span>
<span style="white-space:pre">	</span>assign led_out = rled_out;
endmodule

led3_module.v

module led3_module
(
    clk, rst_n, led_out
);

    input clk;
    input rst_n;
    output led_out;
    
    parameter T10MS = 25'd20_000_000;
    
    reg [24:0] count;
    
    always @(posedge clk or negedge rst_n)
        if (!rst_n)
            count <= 25'd0;
        else if (count == T10MS)
            count <= 25'd0;
        else
            count <= count + 1'b1;
            
    reg rled_out;

    always @(posedge clk or negedge rst_n)
        if (!rst_n)
            rled_out <= 1'b0;
        else if (count >= 25'd15_000_000 && count < 25'd20_000_000)
            rled_out <= 1'b1;
        else
            rled_out <= 1'b0;
            
    assign led_out = rled_out;

endmodule

主程序 forever_led.v

module forever_led
(
<span style="white-space:pre">	</span>clock_50,key,ledg
);
<span style="white-space:pre">	</span>input clock_50;
<span style="white-space:pre">	</span>input [0:0] key;
<span style="white-space:pre">	</span>output [3:0] ledg;
<span style="white-space:pre">	</span>
<span style="white-space:pre">	</span>wire led0_out;
<span style="white-space:pre">	</span>led0_mudule U0
<span style="white-space:pre">	</span>(
<span style="white-space:pre">	</span>.clk(clock_50),
<span style="white-space:pre">	</span>.rst_n(key),
<span style="white-space:pre">	</span>.led_out(led0_out)
<span style="white-space:pre">	</span>);
<span style="white-space:pre">	</span>
<span style="white-space:pre">	</span>wire led1_out;
<span style="white-space:pre">	</span>led1_mudule U1
<span style="white-space:pre">	</span>(
<span style="white-space:pre">	</span>.clk(clock_50),
<span style="white-space:pre">	</span>.rst_n(key),
<span style="white-space:pre">	</span>.led_out(led1_out)
<span style="white-space:pre">	</span>);
<span style="white-space:pre">	</span>
<span style="white-space:pre">	</span>wire led2_out;
<span style="white-space:pre">	</span>led2_mudule U2
<span style="white-space:pre">	</span>(
<span style="white-space:pre">	</span>.clk(clock_50),
<span style="white-space:pre">	</span>.rst_n(key),
<span style="white-space:pre">	</span>.led_out(led2_out)
<span style="white-space:pre">	</span>);
<span style="white-space:pre">		</span>
<span style="white-space:pre">	</span>wire led3_out;
<span style="white-space:pre">	</span>led3_mudule U3
<span style="white-space:pre">	</span>(
<span style="white-space:pre">	</span>.clk(clock_50),
<span style="white-space:pre">	</span>.rst_n(key),
<span style="white-space:pre">	</span>.led_out(led3_out)
<span style="white-space:pre">	</span>);<span style="white-space:pre">	</span>
<span style="white-space:pre">	</span>
<span style="white-space:pre">	</span>assign ledg[3:0]={led0_out,led1_out,led2_out,led3_out};
<span style="white-space:pre">	</span>
endmodule

我得DE2 引脚分配图：



下载进去后就能看到4个不同延时的LED灯闪烁，再次强调是并行的关系~