protel99 学习笔记

1导入网络表出现错误： Add node D1-2 to net GND Error: Node Not found

同2

2:二极管封装与原理图中的元件，管脚标号不一致，封装管脚标号改成A和K

3：http://blog.sina.com.cn/s/blog_59b8fbe90100ds6h.html

4：PCB第一次错误：

Protel Design System Design Rule Check

PCB File : Documents\PCB1.PCB

Date : 1-Jul-2015

Time : 00:22:52

Processing Rule : Room Sheet1 (Region = (49999.5mil, 49999.5mil, 51999.5mil, 51999.5mil) (Is part of Component class Sheet1 )

Violation between Component Y1(28680mil,26540mil) TopLayer and

Room Sheet1 (Region = (49999.5mil, 49999.5mil, 51999.5mil, 51999.5mil) (Is part of Component class Sheet1 )

Violation between Component U1(28928.987mil,28186.981mil) TopLayer and

Room Sheet1 (Region = (49999.5mil, 49999.5mil, 51999.5mil, 51999.5mil) (Is part of Component class Sheet1 )

Violation between Component J1(27240mil,26120mil) TopLayer and

Room Sheet1 (Region = (49999.5mil, 49999.5mil, 51999.5mil, 51999.5mil) (Is part of Component class Sheet1 )

Violation between Component D1(27620mil,26360mil) TopLayer and

Room Sheet1 (Region = (49999.5mil, 49999.5mil, 51999.5mil, 51999.5mil) (Is part of Component class Sheet1 )

Violation between Component C2(28260mil,26280mil) TopLayer and

Room Sheet1 (Region = (49999.5mil, 49999.5mil, 51999.5mil, 51999.5mil) (Is part of Component class Sheet1 )

Violation between Component C1(28260mil,26580mil) TopLayer and

Room Sheet1 (Region = (49999.5mil, 49999.5mil, 51999.5mil, 51999.5mil) (Is part of Component class Sheet1 )

Rule Violations :6

Processing Rule : Hole Size Constraint (Min=1mil) (Max=100mil) (On the board )

Rule Violations :0

Processing Rule : Width Constraint (Min=10mil) (Max=10mil) (Prefered=10mil) (On the board )

Rule Violations :0

Processing Rule : Clearance Constraint (Gap=10mil) (On the board ),(On the board )

Violation between Track (30000mil,26000mil)(30000mil,28620mil) TopLayer and

Track (27420mil,26040mil)(30140mil,26040mil) TopLayer

Rule Violations :1

Processing Rule : Broken-Net Constraint ( (On the board ) )

Violation Net VCC is broken into 3 sub-nets. Routed To 0.00%

Subnet : J1-2

Subnet : D1-1

Subnet : U1-40

Rule Violations :1

Processing Rule : Short-Circuit Constraint (Allowed=Not Allowed) (On the board ),(On the board )

Violation between Track (30000mil,26000mil)(30000mil,28620mil) TopLayer and

Track (27420mil,26040mil)(30140mil,26040mil) TopLayer

Rule Violations :1

Violations Detected : 9

Time Elapsed : 00:00:00



5 ERC检验错误

#1 Warning   Unconnected Input Pin On Net NetU_9
Sheet1.Sch(U-9 @700,650)

#3 Error   Floating Input Pins On Net NetU_9
Pin Sheet1.Sch(U-9 @700,650)

#4 Warning   Unconnected Input Pin On Net NetU_19
Sheet1.Sch(U-19 @700,640)

#6 Error   Floating Input Pins On Net NetU_19
Pin Sheet1.Sch(U-19 @700,640)

#7 Warning   Unconnected Input Pin On Net NetU_31
Sheet1.Sch(U-31 @700,630)

#9 Error   Floating Input Pins On Net NetU_31
Pin Sheet1.Sch(U-31 @700,630)

解决办法：把三个引脚的属性改成了passive

6:[b]protel 99se 封装时出现footprint not found in library[/b]

元件的封装没有找到

其他的些错误及解决方法

floating input pins on net DDR-A0：连接线的时候没有连接到元件的端点。

unconnected net label on net DDR-D0

把label没有放置正确，放的时候出现一个圆点的时候才算放好

output pins and power pins on net net U32-M2

输出端子和电源接在一起

unconnected input pins on net B.EM-A10线没有连接好，放置导线的时候。

Multiple output pins on net U14-2 我也在研究

Action;Add node DC2-39 to net ATA.IORDY Error:node not found：元件的引脚名和封装引脚的引脚名不一致，比如二极管元件引脚是A和K，封装是1和2.

component not found：元件设置的封装名和PCB的通用封装名不一致；比如元件封装设置为DIP-14，而通用封装是DIP14。

追问：

PCD通用封装名是什么，在哪里看啊，怎么设置？

我用的CON3出现的问题，就改了个text应该不会影响吧。还有part里面的footprint是什么意思。

出现的错误

Macro 1: New Component

Add new component A7

Error: Footprint not found in library

Macro 2: New Node

Add node A7-1 to net NetA7_1

Error: Component not found

Macro 3: New Node

Add node A7-2 to net SGND

Error: Component not found

Macro 4: New Node

Add node A7-3 to net NetA7_3

Error: Component not found

7: Net XTAL1 is broken into 2 sub-nets. Routed To 50.00% PCB检查规则

就是你有一根飞线还没有连，仔细看下，你可以看出来，我也是遇到同样的情况。

你可以把文档的栅格线改成星点线，这样容易看出来是哪里的飞线没有连。