CQU数字逻辑实验——交通灯系统设计

module lights(out,an,led,clk,rst_n);
input wire clk,rst_n;//时钟和重置键
output reg [5:0] led;//led灯显示接口
output  reg [6:0] out;//数码管显示接口
output  reg [3:0] an; //控制数码管开关
//============================================================
reg newclk;
reg [30:0] count2;

parameter s0=3'd0,//没有输出
s1=3'd1,//输出100001
s2=3'd2,//输出010010
s3=3'd3,//输出001100
s4=3'd4;//输出010010
reg [3:0] count; //计时用
reg [2:0] pstate,nstate;    //原状态，现状态
//============================================================
//状态转换1（次态到现态转换的条件）
always @ (posedge newclk or negedge rst_n)
begin
if(!rst_n)
begin
pstate<=s0;
count<=0;
end
else
begin
if((pstate==s1)||(pstate==s3))
begin
count<=count+1;
if(count==8)
begin
pstate<=nstate;
count<=5;//当状态为s2和s4时要倒数4秒
end
end
else if(pstate==s2 || pstate==s4)
begin
count<=count+1;
if(count==8)
begin
pstate<=nstate;
count<=0;//当状态为s2和s4时要倒数9秒
end
end
else
pstate<=nstate;
end
end
//============================================================
//状态转换2 (现态的赋值)
always @ (pstate or rst_n)
begin
case(pstate)
s0: if(rst_n==1)
nstate=s1;
else
nstate=s0;
s1: nstate=s2;
s2: nstate=s3;
s3: nstate=s4;
s4: nstate=s1;
default:nstate=s0;
endcase
end
//============================================================
//led灯显示
always @ (pstate or rst_n)
begin
if(pstate==s1)
led=6'b100_001;
else if(pstate==s2)
led=6'b010_010;
else if(pstate==s3)
led=6'b001_100;
else if(pstate==s4)
led=6'b010_010;
else
led=6'b000_000;
end
//===========================================================
//时钟转换
always@(posedge clk)
begin
if(!rst_n) begin
count2<=0;
newclk<=0;   //初始化
end
else begin
count2<=count2+1;
if(count2==25000000)//控制时间间隔
begin
newclk<=~newclk;
count2<=0;
end
end
end
//===========================================================
//数字时钟显示
always@(count)
begin
case(count)
0:out=7'b0000100;//9
1:out=7'b0000000;//8
2:out=7'b0001111;//7
3:out=7'b0100000;//6
4:out=7'b0100100;//5
5:out=7'b1001100;//4
6:out=7'b0000110;//3
7:out=7'b0010010;//2
8:out=7'b1001111;//1
9:out=7'b0000001;//0
default:out=0;
endcase
end
always @ ( * ) begin
if(rst_n==1)
an = 4'b1110;//前三个1用于使前三个灯灭，状态为0时亮
else
an = 4'b1111;
end
endmodule

`timescale 10ns / 10ns
module test( );
reg clk;
reg rst_n;
wire [5:0] led;
wire [6:0] digi;
wire [3:0] an;
lights t1(digi,an,led,clk,rst_n);
initial
begin
clk=0;
rst_n=0;
#100000000 rst_n=1;
#1000000000 rst_n=0;
#300000000 rst_n=1;
end

always
#1 clk = ~clk;

set_property IOSTANDARD LVCMOS33 [get_ports rst_n]
set_property IOSTANDARD LVCMOS33 [get_ports clk]
set_property IOSTANDARD LVCMOS33 [get_ports {out[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {out[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {out[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {out[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {out[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {out[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {out[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {an[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {an[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {an[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {an[0]}]
set_property PACKAGE_PIN W5 [get_ports clk]
set_property PACKAGE_PIN V17 [get_ports rst_n]
set_property PACKAGE_PIN U16 [get_ports {led[0]}]
set_property PACKAGE_PIN E19 [get_ports {led[1]}]
set_property PACKAGE_PIN U19 [get_ports {led[2]}]
set_property PACKAGE_PIN V19 [get_ports {led[3]}]
set_property PACKAGE_PIN W18 [get_ports {led[4]}]
set_property PACKAGE_PIN U15 [get_ports {led[5]}]
set_property PACKAGE_PIN U2 [get_ports {an[0]}]
set_property PACKAGE_PIN U4 [get_ports {an[1]}]
set_property PACKAGE_PIN V4 [get_ports {an[2]}]
set_property PACKAGE_PIN W4 [get_ports {an[3]}]
set_property PACKAGE_PIN U7 [get_ports {out[0]}]
set_property PACKAGE_PIN V5 [get_ports {out[1]}]
set_property PACKAGE_PIN U5 [get_ports {out[2]}]
set_property PACKAGE_PIN V8 [get_ports {out[3]}]
set_property PACKAGE_PIN U8 [get_ports {out[4]}]
set_property PACKAGE_PIN W6 [get_ports {out[5]}]
set_property PACKAGE_PIN W7 [get_ports {out[6]}]

时钟分频器
//Example 62b: clock divider
module clkdiv(
input wire clk,
input wire clr,
output wire clk3
);
reg [24:0] q;
// 25-bit counter
always @(posedge clk or posedge clr) begin
if(clr == 1)
q <= 0;
else
q <= q + 1;
end
assign clk3 = q[24]; // 3 Hz
endmodule

module divi(clk,rst,newclk);
input clk;
input rst;
output newclk;
reg newclk;
reg [30:0] count;
always@(posedge clk)
begin
if(!rst) begin
count<=0;
newclk<=0;   //初始化
end
else begin
count<=count+1;
if(count==25000000)
begin
newclk<=~newclk;
count<=0;
end
end
end
endmodule</span>

//例15a：x7seg：显示4位的十六进制数
module x7seg (
input wire [15:0] x,
input wire clk,
input wire clr,
output reg [6:0] a_to_g,
output reg [3:0] an
//output wire dp
);
wire [1:0] s;
reg [3:0] digit;
wire [3:0] aen;
reg [19:0] clkdiv;
//assign dp = 1;
assign s = clkdiv[19:18]; // count every 5.2 ms
assign aen = 4' b1111; // enable all digits
// 4位 4选1 MUX: mux44
always @ ( * ) case (s)
0: digit = x[3:0];
1: digit = x[7:4];
2: digit = x[11:8];
3: digit = x[15:12];
default: digit = x[3:0];
endcase
// 7段数码管：hex7seg
always @ ( * ) case (digit)
0: a_to_g = 7'b0000001;
1: a_to_g = 7'b1001111;
2: a_to_g = 7'b0010010;
3: a_to_g = 7'b0000110;
4: a_to_g = 7'b1001100;
5: a_to_g = 7'b0100100;
6: a_to_g = 7'b0100000;
7: a_to_g = 7'b0001111;
8: a_to_g = 7'b0000000;
9: a_to_g = 7'b0000100;
'hA: a_to_g = 7'b0001000;
'hB: a_to_g = 7'b1100000;
'hC: a_to_g = 7'b0110001;
'hD: a_to_g = 7'b1000010;
'hE: a_to_g = 7'b0110000;
'hF: a_to_g = 7'b0111000;
default: a_to_g = 7'b0000001; // 0
endcase
// Digit select: ancode
always @ ( * ) begin
an = 4'b1111;
if (aen[s] == 1)
an[s] = 0;
end
// 时钟分频器
always @ (posedge clk or posedge clr) begin
if (clr == 1)
clkdiv <= 0;
else
clkdiv <= clkdiv + 1;
end
endmodule

module display(in,out,sel);
input [3:0]  in;
output [6:0] out;
output  sel;
reg [6:0] out;
always@(in)
begin
case(in)
0:out=7'b1111_110;
1:out=7'b0110_000;
2:out=7'b1101_101;
3:out=7'b1111_001;
4:out=7'b0110_011;
5:out=7'b1011_011;
6:out=7'b1011_111;
7:out=7'b1110_000;
8:out=7'b1111_111;
9:out=7'b1111_011;
default:out=0;
endcase
end
assign sel=0;  //控制四个并排的四个七段数码管哪一个亮
endmodule

module top(rst,clk,out,sel,b);
input rst;
input clk;
output sel，b;
output [6:0]out;
wire b;
wire [3:0] data;
divi a1(clk,rst,b);
counter a3(b,rst,data);
display a2(data,out,sel);
endmodule

module divi(clk,rst,newclk);
input clk;
input rst;
output newclk;
reg newclk;
reg [30:0] count;
always@(posedge clk)
begin
if(!rst) begin
count<=0;
newclk<=0;   //初始化
end
else begin
count<=count+1;
if(count==25000000)
begin
newclk<=~newclk;
count<=0;
end
end
end
endmodule

module counter(clk,rst,out);
input rst;
input clk;
output [3:0]out;
reg [3:0] out;
always@(posedge clk) begin
if(!rst)
out<=0;
else begin
out<=out+1;
if(out==10) out<=0;
end
end
endmodule

module display(in,out,sel);
input [3:0]  in;
output [6:0] out;
output  sel;
reg [6:0] out;
always@(in)
begin
case(in)
0:out=7'b1111_110;
1:out=7'b0110_000;
2:out=7'b1101_101;
3:out=7'b1111_001;
4:out=7'b0110_011;
5:out=7'b1011_011;
6:out=7'b1011_111;
7:out=7'b1110_000;
8:out=7'b1111_111;
9:out=7'b1111_011;
default:out=0;
endcase
end
assign sel=0;  //控制四个并排的四个七段数码管哪一个亮
endmodule