求大神指导，ISE Verilog程序综合的error不知如何解决，又被虐了。

程序是实现一个数字钟，有进位、清零功能。数字钟的分钟和小时是用数码管显示，秒信号是用LED显示8421BCD码。
很多变量都有这种error：The logic for <secondL> does not match a known FF or Latch template. The description style you are using to describe a register or latch is not supported
in the current software release.

module DigitalClk(
input clk,
input clr,
input th,
input tm,
output reg[3:0]secondL,
output reg[3:0]secondH,
output reg[6:0]a_to_g,
output reg[3:0]an

);
reg [3:0]minuteL;
reg [3:0]minuteH;
reg [3:0]hourH;
reg [3:0]hourL;
reg [5:0]minut;
reg [4:0]hour;
reg [5:0]sec;
reg [26:0]counter;
reg [1:0]s;
reg [3:0]digit;
integer i;
initial
begin
secondL<=0;
secondH<=0;
minuteL<=0;
minuteH<=0;
hourL<=0;
hourH<=0;
minut<=0;
hour<=0;
sec<=0;
end

always@(*)

begin
an=4'b1111;
s<=counter[26:25];
an[s]=0;

case(s)
0:digit<=minuteL;
1:digit<=minuteH;
2:digit<=hourL;
3:digit<=hourH;
default:digit<=minuteL;
endcase
case(digit)
0:a_to_g=7'b0000001;
1:a_to_g=7'b1001111;
2:a_to_g=7'b0010010;
3:a_to_g=7'b0000110;
4:a_to_g=7'b1001100;
5:a_to_g=7'b0100100;
6:a_to_g=7'b0100000;
7:a_to_g=7'b0001111;
8:a_to_g=7'b0000000;
9:a_to_g=7'b0001100;
'hA:a_to_g=7'b0001000;
'hB:a_to_g=7'b1100000;
'hC:a_to_g=7'b0110001;
'hD:a_to_g=7'b1000010;
'hE:a_to_g=7'b0110000;
'hF:a_to_g=7'b0111000;
default:a_to_g=7'b0000001;
endcase
end
always@(posedge clk or posedge clr)
begin
if(clr==1)
begin
secondL<=0;
secondH<=0;
minuteL<=0;
minuteH<=0;
hourL<=0;
hourH<=0;
minut<=0;
hour<=0;
sec<=0;
end
if(tm==1)
begin
if(minut==59)
begin
minut<=0;
if(hour==23)
begin
hour<=0;
end
else
begin
hour<=hour+1;
end
end
else
begin
minut<=minut+1;
end
for(i=0;i<6;i=i+1)
begin
if(minut[5:0]-i*10<10)
begin
minuteH<=i;
minuteL<=minut[5:0]-i*10;
i=6;
end
end
for(i=0;i<3;i=i+1)
begin
if(hour[4:0]-i*10<10)
begin
hourH<=i;
hourL<=hour[4:0]-i*10;
i=6;
end
end
end
if(th==1)
begin
if(hour==23)
begin
hour<=0;
minut<=0;
minuteH<=0;
minuteL<=0;
end
else
begin
hour<=hour+1;
end
for(i=0;i<3;i=i+1)
begin
if(hour[4:0]-i*10<10)
begin
hourH<=i;
hourL<=hour[4:0]-i*10;
i=6;
end
end
end
else if(counter==50000000)
begin
counter<=0;
if(sec==59)
begin
sec<=0;
minut<=minut+1;
if(minut==59)
begin
minut<=0;
if(hour==23)
begin
hour<=0;
end
else if(hour<23)
begin
hour<=hour+1;
end
end
else if(minut<59)
begin
minut<=minut+1;
end
end
for(i=0;i<6;i=i+1)
begin
if(sec[5:0]-i*10<10)
begin
secondH<=i;
secondL<=sec[5:0]-i*10;
i=6;
end
end
for(i=0;i<6;i=i+1)
begin
if(minut[5:0]-i*10<10)
begin
minuteH<=i;
minuteL<=minut[5:0]-i*10;
i=6;
end
end
for(i=0;i<3;i=i+1)
begin
if(hour[4:0]-i*10<10)
begin
hourH<=i;
hourL<=hour[4:0]-i*10;
end
end
end
counter<=counter+1;
end
endmodule