1 学习笔记——start.S文件分析

版本号：uboot 2010.06
汇编语言详细分析
start.S文件在\arch\arm\cpu\arm926ejs目录下

#include <config.h>
#include <common.h>
#include <version.h>

#if defined(CONFIG_OMAP1610)
#include <./configs/omap1510.h>
#elif defined(CONFIG_OMAP730)
#include <./configs/omap730.h>
#endif //此段和OMAP板子的移植有关系，这里不用
/************************************************************************
*Jump vector table as in table 3.1 in [1]向量表的填写
*************************************************************************/
.globl _start //定义全局变量
_start://上电开始执行第一句
b reset
#ifdef CONFIG_PRELOADER //9260中未定义，故不用分析
/* No exception handlersin preloader */
ldr pc, _hang
ldr pc, _hang
ldr pc, _hang
ldr pc, _hang
ldr pc, _hang
ldr pc, _hang
ldr pc, _hang
_hang:
.word do_hang
/* pad to 64 byteboundary */
.word 0x12345678
.word 0x12345678
.word 0x12345678
.word 0x12345678
.word 0x12345678
.word 0x12345678
.word 0x12345678
#else
ldr pc, _undefined_instruction//安装向量表
ldr pc, _software_interrupt
ldr pc, _prefetch_abort
ldr pc, _data_abort
ldr pc, _not_used
ldr pc, _irq
ldr pc, _fiq
_undefined_instruction:
.wordundefined_instruction
_software_interrupt:
.wordsoftware_interrupt
_prefetch_abort:
.wordprefetch_abort
_data_abort:
.worddata_abort
_not_used:
.wordnot_used
_irq:
.wordirq
_fiq:
.wordfiq
#endif /*CONFIG_PRELOADER */
.balignl16,0xdeadbeef
/**************************************************************************
*Startup Code (reset vector)
* doimportant init only if we don't start from memory!
*setup Memory and board specific bits prior to relocation.
*relocate armboot to ram
*setup stack
**************************************************************************/
_TEXT_BASE: //标号TEXT_BASE = 0x23f00000
.word TEXT_BASE
.globl _armboot_start
_armboot_start:
.word _start
/* These are defined in the board-specificlinker script.*/
.globl _bss_start
_bss_start:
.word__bss_start
.globl _bss_end
_bss_end:
.word_end
#ifdef CONFIG_USE_IRQ
/* IRQ stack memory(calculated at run-time) */
.globl IRQ_STACK_START
IRQ_STACK_START:
.word 0x0badc0de
/* IRQ stack memory(calculated at run-time) */
.globl FIQ_STACK_START
FIQ_STACK_START:
.word 0x0badc0de
#endif
/* the actual reset code*/

reset:
/*setthe cpu to SVC32 mode*/
mrs r0,cpsr //传送CPSR的内容到R0
bic r0,r0,#0x1f//位清零 r0=xxx0 0000
orr r0,r0,#0xd3 //逻辑位 或 r0=11x1 xx11 经过以上两步后R0=11X1 0011
msr cpsr,r0 //传送R0的内容到CPSR
/**we do sys-critical inits only at reboot,not when booting from ram!*/
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
bl cpu_init_crit// BL跳转指令，但跳转之前，会在寄存器R14中保存PC的当前内容
#endif
#ifndef CONFIG_SKIP_RELOCATE_UBOOT
relocate: /*relocate U-Boot to RAM */
adr r0, _start /*r0 <- current position of code */
ldr r1, _TEXT_BASE /* test if we run from flash or RAM */
cmp r0, r1 /* don't reloc duringdebug */
beq stack_setup
ldr r2, _armboot_start
ldr r3, _bss_start
sub r2, r3, r2 /*r2 <- size of armboot */
add r2, r0, r2 /*r2 <- source end address */
copy_loop:
ldmia r0!, {r3-r10} /* copy from source address [r0] */
stmia r1!, {r3-r10} /* copy to targetaddress [r1] */
cmp r0, r2 /*until source end addreee [r2] */
ble copy_loop
#endif /*CONFIG_SKIP_RELOCATE_UBOOT */
/*Set up the stack */
stack_setup:
ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */
sub sp, r0, #128 /*leave 32 words for abort-stack */
#ifndef CONFIG_PRELOADER
sub r0, r0,#CONFIG_SYS_MALLOC_LEN /* mallocarea */
sub r0, r0, #CONFIG_SYS_GBL_DATA_SIZE/* bdinfo */
#ifdef CONFIG_USE_IRQ
sub r0, r0,#(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
#endif
#endif /*CONFIG_PRELOADER */
sub sp, r0, #12 /*leave 3 words for abort-stack */
bic sp, sp, #7 /*8-byte alignment for ABI compliance */
clear_bss:
ldr r0, _bss_start /* find start of bss segment */
ldr r1, _bss_end /*stop here */
mov r2, #0x00000000 /*clear */
#ifndef CONFIG_PRELOADER
clbss_l:str r2, [r0] /*clear loop... */
add r0, r0, #4
cmp r0, r1
ble clbss_l
bl coloured_LED_init
bl red_LED_on
#endif /*CONFIG_PRELOADER */
ldr pc, _start_armboot
_start_armboot:
#ifdef CONFIG_NAND_SPL
.word nand_boot
#else
.wordstart_armboot
#endif /* CONFIG_NAND_SPL */
/***************
* CPU_init_critical registers
* setup important registers
* setup memory timing
****************/
#ifndef CONFIG_SKIP_LOWLEVEL_INIT //9260 h文件中有定义
cpu_init_crit:
/**flush v4 I/D caches*/
mov r0, #0
mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
/**disable MMU stuff and caches*/
mrc p15, 0, r0, c1, c0, 0
bic r0, r0, #0x00002300 /* clear bits 13, 9:8 (--V- --RS) */
bic r0, r0, #0x00000087 /* clear bits 7, 2:0 (B--- -CAM)*/
orr r0, r0, #0x00000002 /* set bit 2 (A) Align */
orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */
mcr p15, 0, r0, c1, c0, 0 //将R0中数据传送到协处理器P15的寄存器c1和C0中
/**Go setup Memory and board specific bits prior to relocation.*/
mov ip, lr /*perserve link reg across call */
//将lr复制到ip中，保存当前的lr。即是当前的pc值，因为再下一条指令又要进行跳转了
//ip中保存了reset中调用cpu_init_crit的下一条指令地址
bl lowlevel_init /* go setup pll,mux,memory */
mov lr, ip /*restore link *///lowlevel_init返回后，执行这条指令。将ip传给lr
mov pc, lr /*back to my caller */
//再将lr传给pc，这样就回到了reset的下一条指令处
#endif /* CONFIG_SKIP_LOWLEVEL_INIT */

lowlevel_init函数标记在lowlevel_init.S文件中，
在u-boot-2010.06\arch\arm\cpu\arm926ejs\at91目录下
#include <config.h>
#include <asm/arch/hardware.h>
#include <asm/arch/at91_pmc.h>
#include <asm/arch/at91_wdt.h>
#include <asm/arch/at91_pio.h>
#include <asm/arch/at91_matrix.h>
#include <asm/arch/at91sam9_sdramc.h>
#include <asm/arch/at91sam9_smc.h>
#include <asm/arch/at91_rstc.h>
#ifdef CONFIG_AT91_LEGACY
#include <asm/arch/at91sam9_matrix.h>
#endif
#ifndef CONFIG_SYS_MATRIX_EBICSA_VAL
#define CONFIG_SYS_MATRIX_EBICSA_VALCONFIG_SYS_MATRIX_EBI0CSA_VAL
#endif
_TEXT_BASE:
.word TEXT_BASE
.globl lowlevel_init
.type lowlevel_init,function
lowlevel_init:
mov r5, pc /*r5 = POS1 + 4 current */
POS1:
ldr r0, =POS1 /*r0 = POS1 compile */
ldr r2, _TEXT_BASE
sub r0, r0, r2 /*r0 = POS1-_TEXT_BASE (POS1 relative) */
sub r5, r5, r0 /*r0 = TEXT_BASE-1 */
sub r5, r5, #4 /*r1 = text base - current */
/* memory controlconfiguration 1 *///内存控制配置1
ldr r0, =SMRDATA
ldr r2, =SMRDATA1
ldr r1, _TEXT_BASE
sub r0, r0, r1
sub r2, r2, r1
add r0, r0, r5
add r2, r2, r5
0:
/*the address */
ldr r1, [r0], #4
/*the value */
ldr r3, [r0], #4
str r3, [r1]
cmp r2, r0
bne 0b
/*----------------------------------------------------------------------------
*PMC Init Step 1.
* - Check if the PLL is already initialized
*----------------------------------------------------------------------------*/
ldr r1, =(AT91_ASM_PMC_MCKR) //0xfffffc00(AT91_PMC_BASE+ 0x30)
ldr r0, [r1]
and r0, r0, #3
cmp r0, #0
bne PLL_setup_end
/*---------------------------------------------------------------------------
* -Enable the Main Oscillator
*---------------------------------------------------------------------------*/
ldr r1, =(AT91_ASM_PMC_MOR) //(AT91_PMC_BASE +0x20)
ldr r2, =(AT91_ASM_PMC_SR) //(AT91_PMC_BASE + 0x68)
/*Main oscillator Enable register PMC_MOR: */
ldr r0, =CONFIG_SYS_MOR_VAL
str r0, [r1]
/*Reading the PMC Status to detect when the Main Oscillator is enabled */
mov r4, #AT91_PMC_IXR_MOSCS
MOSCS_Loop:
ldr r3, [r2]
and r3, r4, r3
cmp r3, #AT91_PMC_IXR_MOSCS
bne MOSCS_Loop
/* ----------------------------------------------------------------------------
*PMC Init Step 2.
* Setup PLLA
*----------------------------------------------------------------------------*/
ldr r1, =(AT91_ASM_PMC_PLLAR) // (AT91_PMC_BASE+ 0x28)
ldr r0, =CONFIG_SYS_PLLAR_VAL
str r0, [r1]
/*Reading the PMC Status register to detect when the PLLA is locked */
mov r4, #AT91_PMC_IXR_LOCKA
MOSCS_Loop1:
ldr r3, [r2]
and r3, r4, r3
cmp r3, #AT91_PMC_IXR_LOCKA
bne MOSCS_Loop1
/* ----------------------------------------------------------------------------
*PMC Init Step 3.
* - Switch on the Main Oscillator
*----------------------------------------------------------------------------*/
ldr r1, =(AT91_ASM_PMC_MCKR)
/*-Master Clock Controller register PMC_MCKR */
ldr r0, =CONFIG_SYS_MCKR1_VAL
str r0, [r1]
/*Reading the PMC Status to detect when the Master clock is ready */
mov r4, #AT91_PMC_IXR_MCKRDY
MCKRDY_Loop:
ldr r3, [r2]
and r3, r4, r3
cmp r3, #AT91_PMC_IXR_MCKRDY
bne MCKRDY_Loop

ldr r0, =CONFIG_SYS_MCKR2_VAL
str r0, [r1]
/*Reading the PMC Status to detect when the Master clock is ready */
mov r4, #AT91_PMC_IXR_MCKRDY
MCKRDY_Loop1:
ldr r3, [r2]
and r3, r4, r3
cmp r3, #AT91_PMC_IXR_MCKRDY
bne MCKRDY_Loop1
PLL_setup_end:
/* ----------------------------------------------------------------------------
* -memory control configuration 2
*----------------------------------------------------------------------------*/
ldr r0, =(AT91_ASM_SDRAMC_TR) //(AT91_SDRAMC_BASE + 0x04)
ldr r1, [r0]
cmp r1, #0
bne SDRAM_setup_end

ldr r0, =SMRDATA1
ldr r2, =SMRDATA2
ldr r1, _TEXT_BASE
sub r0, r0, r1
sub r2, r2, r1
add r0, r0, r5
add r2, r2, r5
2:
/*the address */
ldr r1, [r0], #4
/*the value */
ldr r3, [r0], #4
str r3, [r1]
cmp r2, r0
bne 2b
SDRAM_setup_end:
/*everything is fine now */
mov pc, lr
.ltorg
SMRDATA:
.wordAT91_ASM_WDT_MR
.wordCONFIG_SYS_WDTC_WDMR_VAL
/*configure PIOx as EBI0 D[16-31] */
#if defined(CONFIG_AT91SAM9263)
….
#elif defined(CONFIG_AT91SAM9260) ||defined(CONFIG_AT91SAM9261) \
||defined(CONFIG_AT91SAM9G20)
.wordAT91_ASM_PIOC_PDR
.wordCONFIG_SYS_PIOC_PDR_VAL1
.wordAT91_ASM_PIOC_PUDR
.wordCONFIG_SYS_PIOC_PPUDR_VAL
#endif
.wordAT91_ASM_MATRIX_CSA0
.wordCONFIG_SYS_MATRIX_EBICSA_VAL
/*flash */
.wordAT91_ASM_SMC_MODE0
.wordCONFIG_SYS_SMC0_MODE0_VAL
.wordAT91_ASM_SMC_CYCLE0
.wordCONFIG_SYS_SMC0_CYCLE0_VAL
.wordAT91_ASM_SMC_PULSE0
.wordCONFIG_SYS_SMC0_PULSE0_VAL
.wordAT91_ASM_SMC_SETUP0
.wordCONFIG_SYS_SMC0_SETUP0_VAL
SMRDATA1:
.wordAT91_ASM_SDRAMC_MR
.wordCONFIG_SYS_SDRC_MR_VAL1
.wordAT91_ASM_SDRAMC_TR
.wordCONFIG_SYS_SDRC_TR_VAL1
.wordAT91_ASM_SDRAMC_CR
.wordCONFIG_SYS_SDRC_CR_VAL
.wordAT91_ASM_SDRAMC_MDR
.wordCONFIG_SYS_SDRC_MDR_VAL
.wordAT91_ASM_SDRAMC_MR
.wordCONFIG_SYS_SDRC_MR_VAL2
.wordAT91_SDRAM_BASE
.wordCONFIG_SYS_SDRAM_VAL1
.wordAT91_ASM_SDRAMC_MR
.wordCONFIG_SYS_SDRC_MR_VAL3
.wordAT91_SDRAM_BASE
.wordCONFIG_SYS_SDRAM_VAL2
.wordAT91_SDRAM_BASE
.wordCONFIG_SYS_SDRAM_VAL3
.wordAT91_SDRAM_BASE
.wordCONFIG_SYS_SDRAM_VAL4
.wordAT91_SDRAM_BASE
.wordCONFIG_SYS_SDRAM_VAL5
.wordAT91_SDRAM_BASE
.wordCONFIG_SYS_SDRAM_VAL6
.wordAT91_SDRAM_BASE
.wordCONFIG_SYS_SDRAM_VAL7
.wordAT91_SDRAM_BASE
.wordCONFIG_SYS_SDRAM_VAL8
.wordAT91_SDRAM_BASE
.wordCONFIG_SYS_SDRAM_VAL9
.wordAT91_ASM_SDRAMC_MR
.wordCONFIG_SYS_SDRC_MR_VAL4
.wordAT91_SDRAM_BASE
.wordCONFIG_SYS_SDRAM_VAL10
.wordAT91_ASM_SDRAMC_MR
.wordCONFIG_SYS_SDRC_MR_VAL5
.wordAT91_SDRAM_BASE
.wordCONFIG_SYS_SDRAM_VAL11
.wordAT91_ASM_SDRAMC_TR
.wordCONFIG_SYS_SDRC_TR_VAL2
.wordAT91_SDRAM_BASE
.wordCONFIG_SYS_SDRAM_VAL12
/*User reset enable*/
.wordAT91_ASM_RSTC_MR
.wordCONFIG_SYS_RSTC_RMR_VAL
#ifdefCONFIG_SYS_MATRIX_MCFG_REMAP
/* MATRIX_MCFG - REMAP all masters */
.word AT91_ASM_MATRIX_MCFG
.word 0x1FF
#endif
SMRDATA2:
.word0