S3C2440裸机驱动--MMU源码分析

/************************************************
NAME      : MMU.C
DESC	  :
Revision  : 1.0
************************************************/

#include "def.h"
#include "option.h"
#include "2440addr.h"
#include "2440lib.h"
#include "2440slib.h"
#include "mmu.h"

// 1) Only the section table is used.
// 2) The cachable/non-cachable area can be changed by MMT_DEFAULT value.
//    The section size is 1MB.

extern char __ENTRY[];

void MMU_Init(void)
{
int i,j;
/*
这段程序不能实现当前堆栈和代码区域的重新映射，假如你
想让存储区域自由映射，需要你自己编写一个细致入微的MMU初始化代码
*/
//========================== IMPORTANT NOTE =========================
//The current stack and code area can't be re-mapped in this routine.
//If you want memory map mapped freely, your own sophiscated MMU
//initialization code is needed.
//===================================================================

MMU_DisableDCache();//禁止数据高速缓存
MMU_DisableICache();//禁止指令高速缓存

//要使用回写操作，一定要对DCache进行清除
//If write-back is used,the DCache should be cleared.
for(i=0;i<64;i++)
for(j=0;j<8;j++)
MMU_CleanInvalidateDCacheIndex((i<<26)|(j<<5));//使整个DCache的数据无效
MMU_InvalidateICache();//使无效整个指令Cache

#if 0
//To complete MMU_Init() fast, Icache may be turned on here.
//为了快速完成MMU_Init(), Icache在这打开。
MMU_EnableICache();
#endif

MMU_DisableMMU();//禁止MMU
MMU_InvalidateTLB();//使快表无效

//MMU_SetMTT(int vaddrStart,int vaddrEnd,int paddrStart,int attr)
//MMU_SetMTT(0x00000000,0x07f00000,0x00000000,RW_CNB);  //bank0
MMU_SetMTT(0x00000000,0x03f00000,(int)__ENTRY,RW_CB);  //bank0
MMU_SetMTT(0x04000000,0x07f00000,0,RW_NCNB);  			//bank0
MMU_SetMTT(0x08000000,0x0ff00000,0x08000000,RW_CNB);  //bank1
MMU_SetMTT(0x10000000,0x17f00000,0x10000000,RW_NCNB); //bank2
MMU_SetMTT(0x18000000,0x1ff00000,0x18000000,RW_NCNB); //bank3
//MMU_SetMTT(0x20000000,0x27f00000,0x20000000,RW_CB); //bank4
MMU_SetMTT(0x20000000,0x27f00000,0x20000000,RW_CNB); //bank4 for STRATA Flash
MMU_SetMTT(0x28000000,0x2ff00000,0x28000000,RW_NCNB); //bank5
//30f00000->30100000, 31000000->30200000
MMU_SetMTT(0x30000000,0x30100000,0x30000000,RW_CB);	  //bank6-1
MMU_SetMTT(0x30200000,0x33e00000,0x30200000,RW_NCNB); //bank6-2
//
MMU_SetMTT(0x33f00000,0x33f00000,0x33f00000,RW_CB);   //bank6-3
MMU_SetMTT(0x38000000,0x3ff00000,0x38000000,RW_NCNB); //bank7

MMU_SetMTT(0x40000000,0x47f00000,0x40000000,RW_NCNB); //SFR
MMU_SetMTT(0x48000000,0x5af00000,0x48000000,RW_NCNB); //SFR
MMU_SetMTT(0x5b000000,0x5b000000,0x5b000000,RW_NCNB); //SFR
MMU_SetMTT(0x5b100000,0xfff00000,0x5b100000,RW_FAULT);//not used

MMU_SetTTBase(_MMUTT_STARTADDRESS);//写转换表基地址到C2
MMU_SetDomain(0x55555550|DOMAIN1_ATTR|DOMAIN0_ATTR);
//DOMAIN1: no_access, DOMAIN0,2~15=client(AP is checked)
//写域访问控制位到C3
MMU_SetProcessId(0x0); //快速上下文切换,禁止? MVA="VA"
MMU_EnableAlignFault();//是否开启地址对齐检查功能

MMU_EnableMMU();//使能MMU
MMU_EnableICache();// 使能ICache

//DCache 必须要打开，当MMU打开时.
MMU_EnableDCache(); //DCache should be turned on after MMU is turned on.
}

// attr=RW_CB,RW_CNB,RW_NCNB,RW_FAULT
void ChangeRomCacheStatus(int attr)
{
int i,j;
MMU_DisableDCache();
MMU_DisableICache();
//If write-back is used,the DCache should be cleared.
for(i=0;i<64;i++)
for(j=0;j<8;j++)
MMU_CleanInvalidateDCacheIndex((i<<26)|(j<<5));
MMU_InvalidateICache();
MMU_DisableMMU();
MMU_InvalidateTLB();
MMU_SetMTT(0x00000000,0x07f00000,0x00000000,attr);	//bank0
MMU_SetMTT(0x08000000,0x0ff00000,0x08000000,attr);	//bank1
MMU_EnableMMU();
MMU_EnableICache();
MMU_EnableDCache();
}

void MMU_SetMTT(int vaddrStart,int vaddrEnd,int paddrStart,int attr)
{
volatile U32 *pTT;//定义了页表的指针
volatile int i,nSec;
pTT=(U32 *)_MMUTT_STARTADDRESS+(vaddrStart>>20);//由于内存块是1M的，写页表的基地址
nSec=(vaddrEnd>>20)-(vaddrStart>>20);// nSec:段大小

//页表存储访问信息和存储块的基地址
//(((paddrStart>>20)+i)<<20) ：对应的物理内存页的地址
// attr：访问权限和缓冲属性
for(i=0;i<=nSec;i++)*pTT++=attr |(((paddrStart>>20)+i)<<20);
}

/************************************************
NAME    : MMU.H
DESC    :
Revision: 1.0
************************************************/

#include "2440slib.h"

#ifndef __MMU_H__
#define __MMU_H__
#ifdef __cplusplus
extern "C" {
#endif

#define DESC_SEC	(0x2|(1<<4))
#define CB		(3<<2)  //cache_on, write_back
#define CNB		(2<<2)  //cache_on, write_through
#define NCB             (1<<2)  //cache_off,WR_BUF on
#define NCNB		(0<<2)  //cache_off,WR_BUF off
#define AP_RW		(3<<10) //supervisor=RW, user=RW
#define AP_RO		(2<<10) //supervisor=RW, user=RO

#define DOMAIN_FAULT	(0x0)
#define DOMAIN_CHK	(0x1)
#define DOMAIN_NOTCHK	(0x3)
#define DOMAIN0		(0x0<<5)
#define DOMAIN1		(0x1<<5)

#define DOMAIN0_ATTR	(DOMAIN_CHK<<0)
#define DOMAIN1_ATTR	(DOMAIN_FAULT<<2)

#define RW_CB		(AP_RW|DOMAIN0|CB|DESC_SEC)
#define RW_CNB		(AP_RW|DOMAIN0|CNB|DESC_SEC)
#define RW_NCNB		(AP_RW|DOMAIN0|NCNB|DESC_SEC)
#define RW_FAULT	(AP_RW|DOMAIN1|NCNB|DESC_SEC)

void MMU_Init(void);
void MMU_SetMTT(int vaddrStart,int vaddrEnd,int paddrStart,int attr);
void ChangeRomCacheStatus(int attr);

#ifdef __cplusplus
}
#endif

#endif /*__MMU_H__*/

//具体.h参数请翻看数据手册，及《ARM体系结构与编程+杜春雷》一书