如何將parallel轉成serial?如何將serial轉成parallel? (SOC) (Verilog) 【转载】

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Abstract
在實務上常常需要將parallel轉成serial，然後再將serial轉成parallel，本文討論如何實現這些功能。

Introduction
使用環境：NC-Verilog 5.4 + Debussy 5.4 v9 + Quartus II 7.2

很 多介面都採用serial傳輸，如I2C、LVDS、mini-LVDS…等，在寫入時必須將parallel資料轉成serial，讀出時又得將 serial轉成parallel，所以是個常用的電路，其原理就是使用shift register來達成，本文將一一討論parallel轉serial，serial轉parallel，也順便討論parallel轉 parallel與serial轉serial。

並進串出 (Parallel In Serial Out)



當load為1且clk rising edge時，parallel data載入至register當中，當load為0且clk rising edge時，register資料依序往前遞移，在最後一個register將資料送出。

p2s.v / Verilog

/*
(C) OOMusou 2009 http://oomusou.cnblogs.com
Filename : p2s.v
Simulator : NC-Verilog 5.4 + Debussy 5.4 v9
Synthesizer : Quartus II 7.2
Description : parallel in serial out rtl
Release : Oct/24/2009 1.0
*/

module p2s (
clk,
rst_n,
load,
pi,
so
);

input clk;
input rst_n;
input load;
input [3:0] pi;
output so;

reg [3:0] r;

always@(posedge clk or negedge rst_n)
if (~rst_n)
r <= 4'h0;
else if (load)
r <= pi;
else
r <= {r, 1'b0};

assign so = r[3];

endmodule
33行

r <= {r, 1'b0};
用Verilog實現shift register有很多種方式，但以33行這種方式最精簡，其他coding style可參考(筆記) 如何將值delay n個clock? (SOC) (Verilog)。

Testbench
p2s_tb.v / Verilog

/*
(C) OOMusou 2009 http://oomusou.cnblogs.com
Filename : p2s_tb.v
Simulator : NC-Verilog 5.4 + Debussy 5.4 v9
Description : parallel in serial out testbench
Release : Oct/24/2009 1.0
*/

`timescale 1ns/1ns
`include "p2s.v"

module p2s_tb;

reg clk;
reg rst_n;
reg load;
reg [3:0] pi;
wire so;

initial begin
load = 1'b0;
pi = 4'h0;
#10;
load <= 1'b1;
pi <= 4'b1010;
#20;
load <= 1'b0;
pi <= 4'h0;
end

initial clk = 1'b0;
always #10 clk = ~clk;

initial begin
rst_n = 1'b0;
#5;
rst_n = 1'b1;
end

initial begin
$fsdbDumpfile("p2s.fsdb");
$fsdbDumpvars(0, p2s_tb);
#150;
$finish;
end

p2s p2s_0 (
.clk(clk),
.rst_n(rst_n),
.load(load),
.pi(pi),
.so(so)
);

endmodule
模擬結果



串進並出 (Serial In Parallel Out)



serial data依序送進shift register，當en為1時，一次將shift register內的資料送進parallel out。

s2p.v / Verilog

/*
(C) OOMusou 2009 http://oomusou.cnblogs.com
Filename : s2p.v
Simulator : NC-Verilog 5.4 + Debussy 5.4 v9
Synthesizer : Quartus II 7.2
Description : serial in parallel out rtl
Release : Oct/24/2009 1.0
*/

module s2p (
clk,
rst_n,
en,
si,
po
);

input clk;
input rst_n;
input en;
input si;
output [3:0] po;

reg [3:0] r;

always@(posedge clk or negedge rst_n)
if (~rst_n)
r <= 8'h0;
else
r <= {r, si};

assign po = (en) ? r : 4'h0;

endmodule
Testbench
s2p_tb.v / Verilog

/*
(C) OOMusou 2009 http://oomusou.cnblogs.com
Filename : p2s_tb.v
Simulator : NC-Verilog 5.4 + Debussy 5.4 v9
Description : serial in parallel out testbench
Release : Oct/24/2009 1.0
*/

`timescale 1ns/1ns
`include "s2p.v"

module s2p_tb;

reg clk;
reg rst_n;
reg en;
reg si;
wire [3:0] po;

initial begin
en = 1'b0;
si = 1'b0;
#10;
// 4'b1010
si = 1'b1;
#20;
si = 1'b0;
#20;
si = 1'b1;
#20;
en = 1'b1;
si = 1'b0;
#20;
en = 1'b0;
si = 1'b0;
end

initial clk = 1'b0;
always #10 clk = ~clk;

initial begin
rst_n = 1'b0;
#5;
rst_n = 1'b1;
end

initial begin
$fsdbDumpfile("s2p.fsdb");
$fsdbDumpvars(0, s2p_tb);
#200;
$finish;
end

s2p s2p_0 (
.clk(clk),
.rst_n(rst_n),
.en(en),
.si(si),
.po(po)
);

endmodule
模擬結果



串進串出 (Serial In Serial Out)
基本上串進串出沒有任何實用功能，只能當成delay n個clk用，與(筆記) 如何將值delay n個clock? (SOC) (Verilog)一樣，只是在此順便提及。

s2s.v / Verilog

/*
(C) OOMusou 2009 http://oomusou.cnblogs.com
Filename : s2p.v
Simulator : NC-Verilog 5.4 + Debussy 5.4 v9
Synthesizer : Quartus II 7.2
Description : serial in serial out rtl
Release : Oct/24/2009 1.0
*/

module s2s (
clk,
rst_n,
si,
so
);

input clk;
input rst_n;
input si;
output so;

reg [3:0] r;

always@(posedge clk or negedge rst_n)
if (~rst_n)
r <= 8'h0;
else
r <= {r, si};

assign so = r[3];

endmodule
Testbench
s2s_tb.v/ Verilog

/*
(C) OOMusou 2009 http://oomusou.cnblogs.com
Filename : s2s_tb.v
Simulator : NC-Verilog 5.4 + Debussy 5.4 v9
Description : serial in serial out testbench
Release : Oct/24/2009 1.0
*/

`timescale 1ns/1ns
`include "s2s.v"

module s2s_tb;

reg clk;
reg rst_n;
reg si;
wire so;

initial begin
si = 1'b0;
#10;
// 4'b1010
si = 1'b1;
#20;
si = 1'b0;
#20;
si = 1'b0;
#20;
si = 1'b1;
end

initial clk = 1'b0;
always #10 clk = ~clk;

initial begin
rst_n = 1'b0;
#5;
rst_n = 1'b1;
end

initial begin
$fsdbDumpfile("s2s.fsdb");
$fsdbDumpvars(0, s2s_tb);
#200;
$finish;
end

s2s s2s_0 (
.clk(clk),
.rst_n(rst_n),
.si(si),
.so(so)
);

endmodule
模擬結果



並進並出 (Parallel In Parallel Out)
並進並出也沒實用功能，只是順便提及。

p2p.v / Verilog

/*
(C) OOMusou 2009 http://oomusou.cnblogs.com
Filename : p2p.v
Simulator : NC-Verilog 5.4 + Debussy 5.4 v9
Synthesizer : Quartus II 7.2
Description : parallel in parallel out rtl
Release : Oct/24/2009 1.0
*/

module p2p (
clk,
rst_n,
pi,
po
);

input clk;
input rst_n;
input [3:0] pi;
output [3:0] po;

reg [3:0] r;

always@(posedge clk or negedge rst_n)
if (~rst_n)
r <= 8'h0;
else
r <= pi;

assign po = r;

endmodule
Testbench
p2p_tb.v / Verilog

/*
(C) OOMusou 2009 http://oomusou.cnblogs.com
Filename : p2p_tb.v
Simulator : NC-Verilog 5.4 + Debussy 5.4 v9
Description : parallel in parallel out testbench
Release : Oct/24/2009 1.0
*/

`timescale 1ns/1ns
`include "p2p.v"

module p2p_tb;

reg clk;
reg rst_n;
reg [3:0] pi;
wire [3:0] po;

initial begin
pi = 4'h0;
#10;
pi <= 4'b1010;
#20;
pi <= 4'b1100;
#20
pi <= 4'h0;
end

initial clk = 1'b0;
always #10 clk = ~clk;

initial begin
rst_n = 1'b0;
#5;
rst_n = 1'b1;
end

initial begin
$fsdbDumpfile("p2p.fsdb");
$fsdbDumpvars(0, p2p_tb);
#100;
$finish;
end

p2p p2p_0 (
.clk(clk),
.rst_n(rst_n),
.pi(pi),
.po(po)
);

endmodule
模擬結果



完整程式碼下載
p2s.7z (parallel in serial out)
s2p.7z (serial in parallel out)
s2s.7z (serial in serial out)
p2p.7z (parallel in parallel out)

See Also
(筆記) 如何將值delay n個clock? (SOC) (Verilog)

Reference
陳慶逸 2008，VHDL數位電路設計實務教本 (使用Quartus II)，儒林圖書公司
鄭信源 2007，Verilog硬體描述語言數位電路，儒林圖書公司