(原創) 如何自己用SOPC Builder建立一個能在DE2上跑μC/OS-II的Nios II系統? (IC Design) (DE2) (Quartus II) (Nios II) (SOPC Builder) (μC/OS-II)
2008-01-10 17:13
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Abstract
很多人跑DE2本身的範例，都可以上μC/OS-II這個作業系統，但只要自己用SOPC Builder建立的Nios II系統，就無法上μC/OS-II，本文示範如何用SOPC Builder手動打造一個在DE2上能跑uC/OS-II的Nios II系統。
使用環境：Quartus II 7.2 SP1 + Nios II 7.2 SP1 + DE2(Cyclone II EP2C35F627C6) + μC/OS-II
Introduction
本文為我較早期的文章，雖然仍有參考價值，不過並非最佳的設計，建議您一併參考(原創) 如何自己用SOPC Builder建立一個能在DE2上跑μC/OS-II的Nios II系統 (SRAM精簡版)? (SOC) (Quartus II) (Nios II) (SOPC Builder) (μC/OS-II) (DE2)
根據Altera原廠的資料，要讓Nios II上μC/OS-II，只要依照Using MicroC/OS-II RTOS with the Nios II Processor Tutorial這份資料照著做即可，不過這份資料有幾個問題：
1.這份資料是Altera為自己的開發版所寫的，儘管你照著步驟做，仍無法在DE2上執行。
2.他使用了已經編譯好的sof檔，若你主要是用於Nios II軟體的開發，可以採用這種方式。若你可能加入自己設計的硬體元件，則勢必重新編譯sof檔，很多人就是因為這樣而無法上μC/OS-II。
在(原創) 如何成功執行『Using μC/OS-II RTOS with the Nios II Processor Tutorial』? (中級) (IC Design) (Quartus II) (Nios II) (μC/OS-II) 中雖然克服了萬難讓Nios II上μC/OS-II了，不用總有個遺憾，為什麼只能用DE2原廠範例的DE2_SD_Card_Audio.sof呢?為什麼不能自己用SOPC Builder建立一個Nios II系統跑uC/OS-II呢?後來在Terasic原廠網站
http://www.terasic.com/downloads/cd-rom/de2/DE2_System_v1.4b.zip
中發現在這個目錄下
\DE2_demonstrations\SOPC_Builder\Reference_Design\DE2_NIOS\
有Terasic原廠所建議的Nios II硬體設計，經過一番研究後，整理出這份文件。
Solution
要讓Nios II軟體跑在on-chip memory並不是不可能，但DE2最多只能有49K的on-chip memory，所以若要讓軟體能跑，必須動一些最佳化的方式讓軟體盡量的小，在(原創) 如何在DE2執行Checksum Master範例 (中級) (IC Design) (DE2) (Quartus II) (Nios II) (SOPC Builder)用過幾個方式從軟體解決，有興趣的人可以參考，本篇主要是從硬體解決，直接將μC/OS-II跑在SRAM上。
Quartus II
使用Quartus II建立一個全新的project
Step 1：
建立一個新project
Error : cpu.instruction_master:"cpu.jtag_debug_module"(0x800..0xfff) overlaps "cfi_flash.s1"(0x0..0x3fffff)
Error : cpu.data_master:"cpu.jtag_debug_module"(0x800..0xfff) overlaps "cfi_flash.s1"(0x0..0x3fffff)
Error : cpu.d_irq:Interrupt number conflict(jtag_uart, timer.irg) on 0
在
Error : cpu.instruction_master:"cpu.jtag_debug_module"(0x800..0xfff) overlaps "cfi_flash.s1"(0x0..0x3fffff)
點兩下，將Reset Vector選擇cfi_flash，Exception Vector選擇sram_16bit_512k_0，按Finish完成
module hello_ucosii (
CLOCK_27, // On Board 27 MHz
CLOCK_50, // On Board 50 MHz
EXT_CLOCK, // External Clock
KEY, // Pushbutton[3:0]
FL_DQ, // FLASH Data bus 8 Bits
FL_ADDR, // FLASH Address bus 20 Bits
FL_WE_N, // FLASH Write Enable
FL_RST_N, // FLASH Reset
FL_OE_N, // FLASH Output Enable
FL_CE_N, // FLASH Chip Enable
SRAM_DQ, // SRAM Data bus 16 Bits
SRAM_ADDR, // SRAM Address bus 18 Bits
SRAM_UB_N, // SRAM High-byte Data Mask
SRAM_LB_N, // SRAM Low-byte Data Mask
SRAM_WE_N, // SRAM Write Enable
SRAM_CE_N, // SRAM Chip Enable
SRAM_OE_N // SRAM Output Enable
);
input CLOCK_27; // On Board 27 MHz
input CLOCK_50; // On Board 50 MHz
input EXT_CLOCK; // External Clock
input [3:0] KEY; // Pushbutton[3:0]
inout [7:0] FL_DQ; // FLASH Data bus 8 Bits
output [21:0] FL_ADDR; // FLASH Address bus 22 Bits
output FL_WE_N; // FLASH Write Enable
output FL_RST_N; // FLASH Reset
output FL_OE_N; // FLASH Output Enable
output FL_CE_N; // FLASH Chip Enable
inout [15:0] SRAM_DQ; // SRAM Data bus 16 Bits
output [17:0] SRAM_ADDR; // SRAM Address bus 18 Bits
output SRAM_UB_N; // SRAM Low-byte Data Mask
output SRAM_LB_N; // SRAM High-byte Data Mask
output SRAM_WE_N; // SRAM Write Enable
output SRAM_CE_N; // SRAM Chip Enable
output SRAM_OE_N; // SRAM Output Enable
wire CPU_CLK;
wire CPU_RESET;
wire CLK_18_4;
wire CLK_25;
// Flash
assign FL_RST_N = 1'b1;
Reset_Delay delay1 (.iRST(KEY[0]),.iCLK(CLOCK_50),.oRESET(CPU_RESET));
SDRAM_PLL PLL1 (.inclk0(CLOCK_50),.c0(DRAM_CLK),.c1(CPU_CLK),.c2(CLK_25));
nios_ii u0 (
// 1) global signals:
.clk(CPU_CLK),
.reset_n(CPU_RESET),
// the_sram_0
.SRAM_ADDR_from_the_sram_16bit_512k_0(SRAM_ADDR),
.SRAM_CE_N_from_the_sram_16bit_512k_0(SRAM_CE_N),
.SRAM_DQ_to_and_from_the_sram_16bit_512k_0(SRAM_DQ),
.SRAM_LB_N_from_the_sram_16bit_512k_0(SRAM_LB_N),
.SRAM_OE_N_from_the_sram_16bit_512k_0(SRAM_OE_N),
.SRAM_UB_N_from_the_sram_16bit_512k_0(SRAM_UB_N),
.SRAM_WE_N_from_the_sram_16bit_512k_0(SRAM_WE_N),
// the_tri_state_bridge_0_avalon_slave
.select_n_to_the_cfi_flash(FL_CE_N),
.address_to_the_cfi_flash(FL_ADDR),
.data_to_and_from_the_cfi_flash(FL_DQ),
.read_n_to_the_cfi_flash(FL_OE_N),
.write_n_to_the_cfi_flash(FL_WE_N)
);
endmodule
56行的Reset_Dealy module和SDRAM_PLL module，我們須自己建立。
Reset_Delay.v
module Reset_Delay(iRST,iCLK,oRESET);
input iCLK;
input iRST;
output reg oRESET;
reg [23:0] Cont;
always@(posedge iCLK or negedge iRST)
begin
if(!iRST)
begin
oRESET <= 1'b0;
Cont <= 24'h0000000;
end
else
begin
if(Cont!=24'hFFFFFF)
begin
Cont <= Cont+1;
oRESET <= 1'b0;
end
else
oRESET <= 1'b1;
end
end
endmodule
SDRAM_PLL.v
1// megafunction wizard: %ALTPLL%
2// GENERATION: STANDARD
3// VERSION: WM1.0
4// MODULE: altpll
5
6// ============================================================
7// File Name: SDRAM_PLL.v
8// Megafunction Name(s):
9// altpll
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 6.0 Build 202 06/20/2006 SP 1 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2006 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module SDRAM_PLL (
inclk0,
c0,
c1,
c2);
input inclk0;
output c0;
output c1;
output c2;
wire [5:0] sub_wire0;
wire [0:0] sub_wire6 = 1'h0;
wire [2:2] sub_wire3 = sub_wire0[2:2];
wire [1:1] sub_wire2 = sub_wire0[1:1];
wire [0:0] sub_wire1 = sub_wire0[0:0];
wire c0 = sub_wire1;
wire c1 = sub_wire2;
wire c2 = sub_wire3;
wire sub_wire4 = inclk0;
altpll altpll_component (
.inclk (sub_wire5),
.clk (sub_wire0),
.activeclock (),
.areset (1'b0),
.clkbad (),
module hello_ucosii (
2 CLOCK_27, // On Board 27 MHz
4 CLOCK_50, // On Board 50 MHz
5 EXT_CLOCK, // External Clock
6 KEY, // Pushbutton[3:0]
8 FL_DQ, // FLASH Data bus 8 Bits
FL_ADDR, // FLASH Address bus 20 Bits
FL_WE_N, // FLASH Write Enable
FL_RST_N, // FLASH Reset
FL_OE_N, // FLASH Output Enable
FL_CE_N, // FLASH Chip Enable
SRAM_DQ, // SRAM Data bus 16 Bits
SRAM_ADDR, // SRAM Address bus 18 Bits
SRAM_UB_N, // SRAM High-byte Data Mask
SRAM_LB_N, // SRAM Low-byte Data Mask
SRAM_WE_N, // SRAM Write Enable
SRAM_CE_N, // SRAM Chip Enable
SRAM_OE_N // SRAM Output Enable
);
input CLOCK_27; // On Board 27 MHz
input CLOCK_50; // On Board 50 MHz
input EXT_CLOCK; // External Clock
input [3:0] KEY; // Pushbutton[3:0]
inout [7:0] FL_DQ; // FLASH Data bus 8 Bits
output [21:0] FL_ADDR; // FLASH Address bus 22 Bits
output FL_WE_N; // FLASH Write Enable
output FL_RST_N; // FLASH Reset
output FL_OE_N; // FLASH Output Enable
output FL_CE_N; // FLASH Chip Enable
inout [15:0] SRAM_DQ; // SRAM Data bus 16 Bits
output [17:0] SRAM_ADDR; // SRAM Address bus 18 Bits
output SRAM_UB_N; // SRAM Low-byte Data Mask
output SRAM_LB_N; // SRAM High-byte Data Mask
output SRAM_WE_N; // SRAM Write Enable
output SRAM_CE_N; // SRAM Chip Enable
output SRAM_OE_N; // SRAM Output Enable
// Flash
assign FL_RST_N = 1'b1;
nios_ii u0 (
// 1) global signals:
.clk(CPU_CLK),
.reset_n(KEY[0]),
// the_sram_0
.SRAM_ADDR_from_the_sram_16bit_512k_0(SRAM_ADDR),
.SRAM_CE_N_from_the_sram_16bit_512k_0(SRAM_CE_N),
.SRAM_DQ_to_and_from_the_sram_16bit_512k_0(SRAM_DQ),
.SRAM_LB_N_from_the_sram_16bit_512k_0(SRAM_LB_N),
.SRAM_OE_N_from_the_sram_16bit_512k_0(SRAM_OE_N),
.SRAM_UB_N_from_the_sram_16bit_512k_0(SRAM_UB_N),
.SRAM_WE_N_from_the_sram_16bit_512k_0(SRAM_WE_N),
// the_tri_state_bridge_0_avalon_slave
.select_n_to_the_cfi_flash(FL_CE_N),
.address_to_the_cfi_flash(FL_ADDR),
.data_to_and_from_the_cfi_flash(FL_DQ),
.read_n_to_the_cfi_flash(FL_OE_N),
.write_n_to_the_cfi_flash(FL_WE_N)
);
endmodule
處理pin腳
Step 1：
pins.tcl
cmp add_assignment "hello_ucosii" "" "CLOCK_27" "LOCATION" "PIN_D13"
cmp add_assignment "hello_ucosii" "" "CLOCK_50" "LOCATION" "PIN_N2"
cmp add_assignment "hello_ucosii" "" "EXT_CLOCK" "LOCATION" "PIN_N26"
cmp add_assignment "hello_ucosii" "" "EXT_CLOCK" "LOCATION" "PIN_N26"
cmp add_assignment "hello_ucosii" "" "KEY[0]" "LOCATION" "PIN_G26"
cmp add_assignment "hello_ucosii" "" "KEY[1]" "LOCATION" "PIN_N23"
cmp add_assignment "hello_ucosii" "" "KEY[2]" "LOCATION" "PIN_P23"
cmp add_assignment "hello_ucosii" "" "KEY[3]" "LOCATION" "PIN_W26"
cmp add_assignment "hello_ucosii" "" "SRAM_ADDR[0]" "LOCATION" "PIN_AE4"
cmp add_assignment "hello_ucosii" "" "SRAM_ADDR[1]" "LOCATION" "PIN_AF4"
cmp add_assignment "hello_ucosii" "" "SRAM_ADDR[2]" "LOCATION" "PIN_AC5"
cmp add_assignment "hello_ucosii" "" "SRAM_ADDR[3]" "LOCATION" "PIN_AC6"
cmp add_assignment "hello_ucosii" "" "SRAM_ADDR[4]" "LOCATION" "PIN_AD4"
cmp add_assignment "hello_ucosii" "" "SRAM_ADDR[5]" "LOCATION" "PIN_AD5"
cmp add_assignment "hello_ucosii" "" "SRAM_ADDR[6]" "LOCATION" "PIN_AE5"
cmp add_assignment "hello_ucosii" "" "SRAM_ADDR[7]" "LOCATION" "PIN_AF5"
cmp add_assignment "hello_ucosii" "" "SRAM_ADDR[8]" "LOCATION" "PIN_AD6"
cmp add_assignment "hello_ucosii" "" "SRAM_ADDR[9]" "LOCATION" "PIN_AD7"
cmp add_assignment "hello_ucosii" "" "SRAM_ADDR[10]" "LOCATION" "PIN_V10"
cmp add_assignment "hello_ucosii" "" "SRAM_ADDR[11]" "LOCATION" "PIN_V9"
cmp add_assignment "hello_ucosii" "" "SRAM_ADDR[12]" "LOCATION" "PIN_AC7"
cmp add_assignment "hello_ucosii" "" "SRAM_ADDR[13]" "LOCATION" "PIN_W8"
cmp add_assignment "hello_ucosii" "" "SRAM_ADDR[14]" "LOCATION" "PIN_W10"
cmp add_assignment "hello_ucosii" "" "SRAM_ADDR[15]" "LOCATION" "PIN_Y10"
cmp add_assignment "hello_ucosii" "" "SRAM_ADDR[16]" "LOCATION" "PIN_AB8"
cmp add_assignment "hello_ucosii" "" "SRAM_ADDR[17]" "LOCATION" "PIN_AC8"
cmp add_assignment "hello_ucosii" "" "SRAM_CE_N" "LOCATION" "PIN_AC11"
cmp add_assignment "hello_ucosii" "" "SRAM_DQ[0]" "LOCATION" "PIN_AD8"
cmp add_assignment "hello_ucosii" "" "SRAM_DQ[1]" "LOCATION" "PIN_AE6"
cmp add_assignment "hello_ucosii" "" "SRAM_DQ[2]" "LOCATION" "PIN_AF6"
cmp add_assignment "hello_ucosii" "" "SRAM_DQ[3]" "LOCATION" "PIN_AA9"
cmp add_assignment "hello_ucosii" "" "SRAM_DQ[4]" "LOCATION" "PIN_AA10"
cmp add_assignment "hello_ucosii" "" "SRAM_DQ[5]" "LOCATION" "PIN_AB10"
cmp add_assignment "hello_ucosii" "" "SRAM_DQ[6]" "LOCATION" "PIN_AA11"
cmp add_assignment "hello_ucosii" "" "SRAM_DQ[7]" "LOCATION" "PIN_Y11"
cmp add_assignment "hello_ucosii" "" "SRAM_DQ[8]" "LOCATION" "PIN_AE7"
cmp add_assignment "hello_ucosii" "" "SRAM_DQ[9]" "LOCATION" "PIN_AF7"
cmp add_assignment "hello_ucosii" "" "SRAM_DQ[10]" "LOCATION" "PIN_AE8"
cmp add_assignment "hello_ucosii" "" "SRAM_DQ[11]" "LOCATION" "PIN_AF8"
cmp add_assignment "hello_ucosii" "" "SRAM_DQ[12]" "LOCATION" "PIN_W11"
cmp add_assignment "hello_ucosii" "" "SRAM_DQ[13]" "LOCATION" "PIN_W12"
cmp add_assignment "hello_ucosii" "" "SRAM_DQ[14]" "LOCATION" "PIN_AC9"
cmp add_assignment "hello_ucosii" "" "SRAM_DQ[15]" "LOCATION" "PIN_AC10"
cmp add_assignment "hello_ucosii" "" "SRAM_LB_N" "LOCATION" "PIN_AE9"
cmp add_assignment "hello_ucosii" "" "SRAM_OE_N" "LOCATION" "PIN_AD10"
cmp add_assignment "hello_ucosii" "" "SRAM_UB_N" "LOCATION" "PIN_AF9"
cmp add_assignment "hello_ucosii" "" "SRAM_WE_N" "LOCATION" "PIN_AE10"
cmp add_assignment "hello_ucosii" "" "FL_CE_N" "LOCATION" "PIN_V17"
cmp add_assignment "hello_ucosii" "" "FL_ADDR[0]" "LOCATION" "PIN_AC18"
cmp add_assignment "hello_ucosii" "" "FL_ADDR[1]" "LOCATION" "PIN_AB18"
cmp add_assignment "hello_ucosii" "" "FL_ADDR[2]" "LOCATION" "PIN_AE19"
cmp add_assignment "hello_ucosii" "" "FL_ADDR[3]" "LOCATION" "PIN_AF19"
cmp add_assignment "hello_ucosii" "" "FL_ADDR[4]" "LOCATION" "PIN_AE18"
cmp add_assignment "hello_ucosii" "" "FL_ADDR[5]" "LOCATION" "PIN_AF18"
cmp add_assignment "hello_ucosii" "" "FL_ADDR[6]" "LOCATION" "PIN_Y16"
cmp add_assignment "hello_ucosii" "" "FL_ADDR[7]" "LOCATION" "PIN_AA16"
cmp add_assignment "hello_ucosii" "" "FL_ADDR[8]" "LOCATION" "PIN_AD17"
cmp add_assignment "hello_ucosii" "" "FL_ADDR[9]" "LOCATION" "PIN_AC17"
cmp add_assignment "hello_ucosii" "" "FL_ADDR[10]" "LOCATION" "PIN_AE17"
cmp add_assignment "hello_ucosii" "" "FL_ADDR[11]" "LOCATION" "PIN_AF17"
cmp add_assignment "hello_ucosii" "" "FL_ADDR[12]" "LOCATION" "PIN_W16"
cmp add_assignment "hello_ucosii" "" "FL_ADDR[13]" "LOCATION" "PIN_W15"
cmp add_assignment "hello_ucosii" "" "FL_ADDR[14]" "LOCATION" "PIN_AC16"
cmp add_assignment "hello_ucosii" "" "FL_ADDR[15]" "LOCATION" "PIN_AD16"
cmp add_assignment "hello_ucosii" "" "FL_ADDR[16]" "LOCATION" "PIN_AE16"
cmp add_assignment "hello_ucosii" "" "FL_ADDR[17]" "LOCATION" "PIN_AC15"
cmp add_assignment "hello_ucosii" "" "FL_ADDR[18]" "LOCATION" "PIN_AB15"
cmp add_assignment "hello_ucosii" "" "FL_ADDR[19]" "LOCATION" "PIN_AA15"
cmp add_assignment "hello_ucosii" "" "FL_ADDR[20]" "LOCATION" "PIN_Y15"
cmp add_assignment "hello_ucosii" "" "FL_ADDR[21]" "LOCATION" "PIN_Y14"
cmp add_assignment "hello_ucosii" "" "FL_DQ[0]" "LOCATION" "PIN_AD19"
cmp add_assignment "hello_ucosii" "" "FL_DQ[1]" "LOCATION" "PIN_AC19"
cmp add_assignment "hello_ucosii" "" "FL_DQ[2]" "LOCATION" "PIN_AF20"
cmp add_assignment "hello_ucosii" "" "FL_DQ[3]" "LOCATION" "PIN_AE20"
cmp add_assignment "hello_ucosii" "" "FL_DQ[4]" "LOCATION" "PIN_AB20"
cmp add_assignment "hello_ucosii" "" "FL_DQ[5]" "LOCATION" "PIN_AC20"
cmp add_assignment "hello_ucosii" "" "FL_DQ[6]" "LOCATION" "PIN_AF21"
cmp add_assignment "hello_ucosii" "" "FL_DQ[7]" "LOCATION" "PIN_AE21"
cmp add_assignment "hello_ucosii" "" "FL_OE_N" "LOCATION" "PIN_W17"
cmp add_assignment "hello_ucosii" "" "FL_WE_N" "LOCATION" "PIN_AA17"
cmp add_assignment "hello_ucosii" "" "FL_RST_N" "LOCATION" "PIN_AA18"
在View->Utility Windows->Tcl Console出現Tcl Console
輸入
source pins.tcl
Step 2：
將沒用到的pin設為tri-state
Menu的Assignment->Device..
按下Device and Pin Options..
選擇Unused Pins tab，將Reserve all unused pins設為 As input tri-stated
至此，Quartus II部分已經完成，可以開始編譯產生.sof檔，這需要很久的時間，完全看你CPU速度而定，編譯完成後燒將hello_ucosii.sof燒進DE2。
Nios II IDE
Step 1：
建立Hello MicroC/OS-II project
Menu:File->New->Nios II C/C++ Application
Step 2：
選擇Hello MicroC/OS-II template，講指定nios_ii.ptf路徑，完成按Finish
Step 3：
執行hello_ucosii_0
選著hello_ucosii_0 project，右鍵Run As->Nios II Hardware
最後執行結果，表示μC/OS-II順利執行
完整程式碼下載
hello_ucosii_sram_big.7z (含SDRAM_PLL.v和Reset_Delay.v)
hello_ucosii_sram_small.7z (不含SDRAM_PLL.v和Reset_Delay.v)
Conclusion
DE2和Altera原廠的版子還是有些差異，很多Altera官方的文件並不適用，在本文又再次證明了這個事實。
See Also
(原創) DE2_NIOS_Lite 1.0 (SOC) (Nios II) (SOPC Builder) (DE2)
(原創) DE2_NIOS_Lite 1.1 (SOC) (Nios II) (SOPC Builder) (μC/OS-II) (DE2)
(原創) 如何自己用SOPC Builder建立一個能在DE2上跑μC/OS-II的Nios II系統 (SRAM精簡版)? (SOC) (Quartus II) (Nios II) (SOPC Builder) (μC/OS-II) (DE2)
(原創) 如何自己用SOPC Builder建立一個能在DE2-70上跑μC/OS-II的Nios II系統? (SOC) (Nios II) (μC/OS-II) (DE2-70)
很多人跑DE2本身的範例，都可以上μC/OS-II這個作業系統，但只要自己用SOPC Builder建立的Nios II系統，就無法上μC/OS-II，本文示範如何用SOPC Builder手動打造一個在DE2上能跑uC/OS-II的Nios II系統。
使用環境：Quartus II 7.2 SP1 + Nios II 7.2 SP1 + DE2(Cyclone II EP2C35F627C6) + μC/OS-II
Introduction
本文為我較早期的文章，雖然仍有參考價值，不過並非最佳的設計，建議您一併參考(原創) 如何自己用SOPC Builder建立一個能在DE2上跑μC/OS-II的Nios II系統 (SRAM精簡版)? (SOC) (Quartus II) (Nios II) (SOPC Builder) (μC/OS-II) (DE2)
根據Altera原廠的資料，要讓Nios II上μC/OS-II，只要依照Using MicroC/OS-II RTOS with the Nios II Processor Tutorial這份資料照著做即可，不過這份資料有幾個問題：
1.這份資料是Altera為自己的開發版所寫的，儘管你照著步驟做，仍無法在DE2上執行。
2.他使用了已經編譯好的sof檔，若你主要是用於Nios II軟體的開發，可以採用這種方式。若你可能加入自己設計的硬體元件，則勢必重新編譯sof檔，很多人就是因為這樣而無法上μC/OS-II。
在(原創) 如何成功執行『Using μC/OS-II RTOS with the Nios II Processor Tutorial』? (中級) (IC Design) (Quartus II) (Nios II) (μC/OS-II) 中雖然克服了萬難讓Nios II上μC/OS-II了，不用總有個遺憾，為什麼只能用DE2原廠範例的DE2_SD_Card_Audio.sof呢?為什麼不能自己用SOPC Builder建立一個Nios II系統跑uC/OS-II呢?後來在Terasic原廠網站
http://www.terasic.com/downloads/cd-rom/de2/DE2_System_v1.4b.zip
中發現在這個目錄下
\DE2_demonstrations\SOPC_Builder\Reference_Design\DE2_NIOS\
有Terasic原廠所建議的Nios II硬體設計，經過一番研究後，整理出這份文件。
Solution
要讓Nios II軟體跑在on-chip memory並不是不可能，但DE2最多只能有49K的on-chip memory，所以若要讓軟體能跑，必須動一些最佳化的方式讓軟體盡量的小，在(原創) 如何在DE2執行Checksum Master範例 (中級) (IC Design) (DE2) (Quartus II) (Nios II) (SOPC Builder)用過幾個方式從軟體解決，有興趣的人可以參考，本篇主要是從硬體解決，直接將μC/OS-II跑在SRAM上。
Quartus II
使用Quartus II建立一個全新的project
Step 1：
建立一個新project
Error : cpu.instruction_master:"cpu.jtag_debug_module"(0x800..0xfff) overlaps "cfi_flash.s1"(0x0..0x3fffff)
Error : cpu.data_master:"cpu.jtag_debug_module"(0x800..0xfff) overlaps "cfi_flash.s1"(0x0..0x3fffff)
Error : cpu.d_irq:Interrupt number conflict(jtag_uart, timer.irg) on 0
在
Error : cpu.instruction_master:"cpu.jtag_debug_module"(0x800..0xfff) overlaps "cfi_flash.s1"(0x0..0x3fffff)
點兩下，將Reset Vector選擇cfi_flash，Exception Vector選擇sram_16bit_512k_0，按Finish完成
module hello_ucosii (
CLOCK_27, // On Board 27 MHz
CLOCK_50, // On Board 50 MHz
EXT_CLOCK, // External Clock
KEY, // Pushbutton[3:0]
FL_DQ, // FLASH Data bus 8 Bits
FL_ADDR, // FLASH Address bus 20 Bits
FL_WE_N, // FLASH Write Enable
FL_RST_N, // FLASH Reset
FL_OE_N, // FLASH Output Enable
FL_CE_N, // FLASH Chip Enable
SRAM_DQ, // SRAM Data bus 16 Bits
SRAM_ADDR, // SRAM Address bus 18 Bits
SRAM_UB_N, // SRAM High-byte Data Mask
SRAM_LB_N, // SRAM Low-byte Data Mask
SRAM_WE_N, // SRAM Write Enable
SRAM_CE_N, // SRAM Chip Enable
SRAM_OE_N // SRAM Output Enable
);
input CLOCK_27; // On Board 27 MHz
input CLOCK_50; // On Board 50 MHz
input EXT_CLOCK; // External Clock
input [3:0] KEY; // Pushbutton[3:0]
inout [7:0] FL_DQ; // FLASH Data bus 8 Bits
output [21:0] FL_ADDR; // FLASH Address bus 22 Bits
output FL_WE_N; // FLASH Write Enable
output FL_RST_N; // FLASH Reset
output FL_OE_N; // FLASH Output Enable
output FL_CE_N; // FLASH Chip Enable
inout [15:0] SRAM_DQ; // SRAM Data bus 16 Bits
output [17:0] SRAM_ADDR; // SRAM Address bus 18 Bits
output SRAM_UB_N; // SRAM Low-byte Data Mask
output SRAM_LB_N; // SRAM High-byte Data Mask
output SRAM_WE_N; // SRAM Write Enable
output SRAM_CE_N; // SRAM Chip Enable
output SRAM_OE_N; // SRAM Output Enable
wire CPU_CLK;
wire CPU_RESET;
wire CLK_18_4;
wire CLK_25;
// Flash
assign FL_RST_N = 1'b1;
Reset_Delay delay1 (.iRST(KEY[0]),.iCLK(CLOCK_50),.oRESET(CPU_RESET));
SDRAM_PLL PLL1 (.inclk0(CLOCK_50),.c0(DRAM_CLK),.c1(CPU_CLK),.c2(CLK_25));
nios_ii u0 (
// 1) global signals:
.clk(CPU_CLK),
.reset_n(CPU_RESET),
// the_sram_0
.SRAM_ADDR_from_the_sram_16bit_512k_0(SRAM_ADDR),
.SRAM_CE_N_from_the_sram_16bit_512k_0(SRAM_CE_N),
.SRAM_DQ_to_and_from_the_sram_16bit_512k_0(SRAM_DQ),
.SRAM_LB_N_from_the_sram_16bit_512k_0(SRAM_LB_N),
.SRAM_OE_N_from_the_sram_16bit_512k_0(SRAM_OE_N),
.SRAM_UB_N_from_the_sram_16bit_512k_0(SRAM_UB_N),
.SRAM_WE_N_from_the_sram_16bit_512k_0(SRAM_WE_N),
// the_tri_state_bridge_0_avalon_slave
.select_n_to_the_cfi_flash(FL_CE_N),
.address_to_the_cfi_flash(FL_ADDR),
.data_to_and_from_the_cfi_flash(FL_DQ),
.read_n_to_the_cfi_flash(FL_OE_N),
.write_n_to_the_cfi_flash(FL_WE_N)
);
endmodule
56行的Reset_Dealy module和SDRAM_PLL module，我們須自己建立。
Reset_Delay.v
module Reset_Delay(iRST,iCLK,oRESET);
input iCLK;
input iRST;
output reg oRESET;
reg [23:0] Cont;
always@(posedge iCLK or negedge iRST)
begin
if(!iRST)
begin
oRESET <= 1'b0;
Cont <= 24'h0000000;
end
else
begin
if(Cont!=24'hFFFFFF)
begin
Cont <= Cont+1;
oRESET <= 1'b0;
end
else
oRESET <= 1'b1;
end
end
endmodule
SDRAM_PLL.v
1// megafunction wizard: %ALTPLL%
2// GENERATION: STANDARD
3// VERSION: WM1.0
4// MODULE: altpll
5
6// ============================================================
7// File Name: SDRAM_PLL.v
8// Megafunction Name(s):
9// altpll
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 6.0 Build 202 06/20/2006 SP 1 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2006 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module SDRAM_PLL (
inclk0,
c0,
c1,
c2);
input inclk0;
output c0;
output c1;
output c2;
wire [5:0] sub_wire0;
wire [0:0] sub_wire6 = 1'h0;
wire [2:2] sub_wire3 = sub_wire0[2:2];
wire [1:1] sub_wire2 = sub_wire0[1:1];
wire [0:0] sub_wire1 = sub_wire0[0:0];
wire c0 = sub_wire1;
wire c1 = sub_wire2;
wire c2 = sub_wire3;
wire sub_wire4 = inclk0;
altpll altpll_component (
.inclk (sub_wire5),
.clk (sub_wire0),
.activeclock (),
.areset (1'b0),
.clkbad (),
module hello_ucosii (
2 CLOCK_27, // On Board 27 MHz
4 CLOCK_50, // On Board 50 MHz
5 EXT_CLOCK, // External Clock
6 KEY, // Pushbutton[3:0]
8 FL_DQ, // FLASH Data bus 8 Bits
FL_ADDR, // FLASH Address bus 20 Bits
FL_WE_N, // FLASH Write Enable
FL_RST_N, // FLASH Reset
FL_OE_N, // FLASH Output Enable
FL_CE_N, // FLASH Chip Enable
SRAM_DQ, // SRAM Data bus 16 Bits
SRAM_ADDR, // SRAM Address bus 18 Bits
SRAM_UB_N, // SRAM High-byte Data Mask
SRAM_LB_N, // SRAM Low-byte Data Mask
SRAM_WE_N, // SRAM Write Enable
SRAM_CE_N, // SRAM Chip Enable
SRAM_OE_N // SRAM Output Enable
);
input CLOCK_27; // On Board 27 MHz
input CLOCK_50; // On Board 50 MHz
input EXT_CLOCK; // External Clock
input [3:0] KEY; // Pushbutton[3:0]
inout [7:0] FL_DQ; // FLASH Data bus 8 Bits
output [21:0] FL_ADDR; // FLASH Address bus 22 Bits
output FL_WE_N; // FLASH Write Enable
output FL_RST_N; // FLASH Reset
output FL_OE_N; // FLASH Output Enable
output FL_CE_N; // FLASH Chip Enable
inout [15:0] SRAM_DQ; // SRAM Data bus 16 Bits
output [17:0] SRAM_ADDR; // SRAM Address bus 18 Bits
output SRAM_UB_N; // SRAM Low-byte Data Mask
output SRAM_LB_N; // SRAM High-byte Data Mask
output SRAM_WE_N; // SRAM Write Enable
output SRAM_CE_N; // SRAM Chip Enable
output SRAM_OE_N; // SRAM Output Enable
// Flash
assign FL_RST_N = 1'b1;
nios_ii u0 (
// 1) global signals:
.clk(CPU_CLK),
.reset_n(KEY[0]),
// the_sram_0
.SRAM_ADDR_from_the_sram_16bit_512k_0(SRAM_ADDR),
.SRAM_CE_N_from_the_sram_16bit_512k_0(SRAM_CE_N),
.SRAM_DQ_to_and_from_the_sram_16bit_512k_0(SRAM_DQ),
.SRAM_LB_N_from_the_sram_16bit_512k_0(SRAM_LB_N),
.SRAM_OE_N_from_the_sram_16bit_512k_0(SRAM_OE_N),
.SRAM_UB_N_from_the_sram_16bit_512k_0(SRAM_UB_N),
.SRAM_WE_N_from_the_sram_16bit_512k_0(SRAM_WE_N),
// the_tri_state_bridge_0_avalon_slave
.select_n_to_the_cfi_flash(FL_CE_N),
.address_to_the_cfi_flash(FL_ADDR),
.data_to_and_from_the_cfi_flash(FL_DQ),
.read_n_to_the_cfi_flash(FL_OE_N),
.write_n_to_the_cfi_flash(FL_WE_N)
);
endmodule
處理pin腳
Step 1：
pins.tcl
cmp add_assignment "hello_ucosii" "" "CLOCK_27" "LOCATION" "PIN_D13"
cmp add_assignment "hello_ucosii" "" "CLOCK_50" "LOCATION" "PIN_N2"
cmp add_assignment "hello_ucosii" "" "EXT_CLOCK" "LOCATION" "PIN_N26"
cmp add_assignment "hello_ucosii" "" "EXT_CLOCK" "LOCATION" "PIN_N26"
cmp add_assignment "hello_ucosii" "" "KEY[0]" "LOCATION" "PIN_G26"
cmp add_assignment "hello_ucosii" "" "KEY[1]" "LOCATION" "PIN_N23"
cmp add_assignment "hello_ucosii" "" "KEY[2]" "LOCATION" "PIN_P23"
cmp add_assignment "hello_ucosii" "" "KEY[3]" "LOCATION" "PIN_W26"
cmp add_assignment "hello_ucosii" "" "SRAM_ADDR[0]" "LOCATION" "PIN_AE4"
cmp add_assignment "hello_ucosii" "" "SRAM_ADDR[1]" "LOCATION" "PIN_AF4"
cmp add_assignment "hello_ucosii" "" "SRAM_ADDR[2]" "LOCATION" "PIN_AC5"
cmp add_assignment "hello_ucosii" "" "SRAM_ADDR[3]" "LOCATION" "PIN_AC6"
cmp add_assignment "hello_ucosii" "" "SRAM_ADDR[4]" "LOCATION" "PIN_AD4"
cmp add_assignment "hello_ucosii" "" "SRAM_ADDR[5]" "LOCATION" "PIN_AD5"
cmp add_assignment "hello_ucosii" "" "SRAM_ADDR[6]" "LOCATION" "PIN_AE5"
cmp add_assignment "hello_ucosii" "" "SRAM_ADDR[7]" "LOCATION" "PIN_AF5"
cmp add_assignment "hello_ucosii" "" "SRAM_ADDR[8]" "LOCATION" "PIN_AD6"
cmp add_assignment "hello_ucosii" "" "SRAM_ADDR[9]" "LOCATION" "PIN_AD7"
cmp add_assignment "hello_ucosii" "" "SRAM_ADDR[10]" "LOCATION" "PIN_V10"
cmp add_assignment "hello_ucosii" "" "SRAM_ADDR[11]" "LOCATION" "PIN_V9"
cmp add_assignment "hello_ucosii" "" "SRAM_ADDR[12]" "LOCATION" "PIN_AC7"
cmp add_assignment "hello_ucosii" "" "SRAM_ADDR[13]" "LOCATION" "PIN_W8"
cmp add_assignment "hello_ucosii" "" "SRAM_ADDR[14]" "LOCATION" "PIN_W10"
cmp add_assignment "hello_ucosii" "" "SRAM_ADDR[15]" "LOCATION" "PIN_Y10"
cmp add_assignment "hello_ucosii" "" "SRAM_ADDR[16]" "LOCATION" "PIN_AB8"
cmp add_assignment "hello_ucosii" "" "SRAM_ADDR[17]" "LOCATION" "PIN_AC8"
cmp add_assignment "hello_ucosii" "" "SRAM_CE_N" "LOCATION" "PIN_AC11"
cmp add_assignment "hello_ucosii" "" "SRAM_DQ[0]" "LOCATION" "PIN_AD8"
cmp add_assignment "hello_ucosii" "" "SRAM_DQ[1]" "LOCATION" "PIN_AE6"
cmp add_assignment "hello_ucosii" "" "SRAM_DQ[2]" "LOCATION" "PIN_AF6"
cmp add_assignment "hello_ucosii" "" "SRAM_DQ[3]" "LOCATION" "PIN_AA9"
cmp add_assignment "hello_ucosii" "" "SRAM_DQ[4]" "LOCATION" "PIN_AA10"
cmp add_assignment "hello_ucosii" "" "SRAM_DQ[5]" "LOCATION" "PIN_AB10"
cmp add_assignment "hello_ucosii" "" "SRAM_DQ[6]" "LOCATION" "PIN_AA11"
cmp add_assignment "hello_ucosii" "" "SRAM_DQ[7]" "LOCATION" "PIN_Y11"
cmp add_assignment "hello_ucosii" "" "SRAM_DQ[8]" "LOCATION" "PIN_AE7"
cmp add_assignment "hello_ucosii" "" "SRAM_DQ[9]" "LOCATION" "PIN_AF7"
cmp add_assignment "hello_ucosii" "" "SRAM_DQ[10]" "LOCATION" "PIN_AE8"
cmp add_assignment "hello_ucosii" "" "SRAM_DQ[11]" "LOCATION" "PIN_AF8"
cmp add_assignment "hello_ucosii" "" "SRAM_DQ[12]" "LOCATION" "PIN_W11"
cmp add_assignment "hello_ucosii" "" "SRAM_DQ[13]" "LOCATION" "PIN_W12"
cmp add_assignment "hello_ucosii" "" "SRAM_DQ[14]" "LOCATION" "PIN_AC9"
cmp add_assignment "hello_ucosii" "" "SRAM_DQ[15]" "LOCATION" "PIN_AC10"
cmp add_assignment "hello_ucosii" "" "SRAM_LB_N" "LOCATION" "PIN_AE9"
cmp add_assignment "hello_ucosii" "" "SRAM_OE_N" "LOCATION" "PIN_AD10"
cmp add_assignment "hello_ucosii" "" "SRAM_UB_N" "LOCATION" "PIN_AF9"
cmp add_assignment "hello_ucosii" "" "SRAM_WE_N" "LOCATION" "PIN_AE10"
cmp add_assignment "hello_ucosii" "" "FL_CE_N" "LOCATION" "PIN_V17"
cmp add_assignment "hello_ucosii" "" "FL_ADDR[0]" "LOCATION" "PIN_AC18"
cmp add_assignment "hello_ucosii" "" "FL_ADDR[1]" "LOCATION" "PIN_AB18"
cmp add_assignment "hello_ucosii" "" "FL_ADDR[2]" "LOCATION" "PIN_AE19"
cmp add_assignment "hello_ucosii" "" "FL_ADDR[3]" "LOCATION" "PIN_AF19"
cmp add_assignment "hello_ucosii" "" "FL_ADDR[4]" "LOCATION" "PIN_AE18"
cmp add_assignment "hello_ucosii" "" "FL_ADDR[5]" "LOCATION" "PIN_AF18"
cmp add_assignment "hello_ucosii" "" "FL_ADDR[6]" "LOCATION" "PIN_Y16"
cmp add_assignment "hello_ucosii" "" "FL_ADDR[7]" "LOCATION" "PIN_AA16"
cmp add_assignment "hello_ucosii" "" "FL_ADDR[8]" "LOCATION" "PIN_AD17"
cmp add_assignment "hello_ucosii" "" "FL_ADDR[9]" "LOCATION" "PIN_AC17"
cmp add_assignment "hello_ucosii" "" "FL_ADDR[10]" "LOCATION" "PIN_AE17"
cmp add_assignment "hello_ucosii" "" "FL_ADDR[11]" "LOCATION" "PIN_AF17"
cmp add_assignment "hello_ucosii" "" "FL_ADDR[12]" "LOCATION" "PIN_W16"
cmp add_assignment "hello_ucosii" "" "FL_ADDR[13]" "LOCATION" "PIN_W15"
cmp add_assignment "hello_ucosii" "" "FL_ADDR[14]" "LOCATION" "PIN_AC16"
cmp add_assignment "hello_ucosii" "" "FL_ADDR[15]" "LOCATION" "PIN_AD16"
cmp add_assignment "hello_ucosii" "" "FL_ADDR[16]" "LOCATION" "PIN_AE16"
cmp add_assignment "hello_ucosii" "" "FL_ADDR[17]" "LOCATION" "PIN_AC15"
cmp add_assignment "hello_ucosii" "" "FL_ADDR[18]" "LOCATION" "PIN_AB15"
cmp add_assignment "hello_ucosii" "" "FL_ADDR[19]" "LOCATION" "PIN_AA15"
cmp add_assignment "hello_ucosii" "" "FL_ADDR[20]" "LOCATION" "PIN_Y15"
cmp add_assignment "hello_ucosii" "" "FL_ADDR[21]" "LOCATION" "PIN_Y14"
cmp add_assignment "hello_ucosii" "" "FL_DQ[0]" "LOCATION" "PIN_AD19"
cmp add_assignment "hello_ucosii" "" "FL_DQ[1]" "LOCATION" "PIN_AC19"
cmp add_assignment "hello_ucosii" "" "FL_DQ[2]" "LOCATION" "PIN_AF20"
cmp add_assignment "hello_ucosii" "" "FL_DQ[3]" "LOCATION" "PIN_AE20"
cmp add_assignment "hello_ucosii" "" "FL_DQ[4]" "LOCATION" "PIN_AB20"
cmp add_assignment "hello_ucosii" "" "FL_DQ[5]" "LOCATION" "PIN_AC20"
cmp add_assignment "hello_ucosii" "" "FL_DQ[6]" "LOCATION" "PIN_AF21"
cmp add_assignment "hello_ucosii" "" "FL_DQ[7]" "LOCATION" "PIN_AE21"
cmp add_assignment "hello_ucosii" "" "FL_OE_N" "LOCATION" "PIN_W17"
cmp add_assignment "hello_ucosii" "" "FL_WE_N" "LOCATION" "PIN_AA17"
cmp add_assignment "hello_ucosii" "" "FL_RST_N" "LOCATION" "PIN_AA18"
在View->Utility Windows->Tcl Console出現Tcl Console
輸入
source pins.tcl
Step 2：
將沒用到的pin設為tri-state
Menu的Assignment->Device..
按下Device and Pin Options..
選擇Unused Pins tab，將Reserve all unused pins設為 As input tri-stated
至此，Quartus II部分已經完成，可以開始編譯產生.sof檔，這需要很久的時間，完全看你CPU速度而定，編譯完成後燒將hello_ucosii.sof燒進DE2。
Nios II IDE
Step 1：
建立Hello MicroC/OS-II project
Menu:File->New->Nios II C/C++ Application
Step 2：
選擇Hello MicroC/OS-II template，講指定nios_ii.ptf路徑，完成按Finish
Step 3：
執行hello_ucosii_0
選著hello_ucosii_0 project，右鍵Run As->Nios II Hardware
最後執行結果，表示μC/OS-II順利執行
完整程式碼下載
hello_ucosii_sram_big.7z (含SDRAM_PLL.v和Reset_Delay.v)
hello_ucosii_sram_small.7z (不含SDRAM_PLL.v和Reset_Delay.v)
Conclusion
DE2和Altera原廠的版子還是有些差異，很多Altera官方的文件並不適用，在本文又再次證明了這個事實。
See Also
(原創) DE2_NIOS_Lite 1.0 (SOC) (Nios II) (SOPC Builder) (DE2)
(原創) DE2_NIOS_Lite 1.1 (SOC) (Nios II) (SOPC Builder) (μC/OS-II) (DE2)
(原創) 如何自己用SOPC Builder建立一個能在DE2上跑μC/OS-II的Nios II系統 (SRAM精簡版)? (SOC) (Quartus II) (Nios II) (SOPC Builder) (μC/OS-II) (DE2)
(原創) 如何自己用SOPC Builder建立一個能在DE2-70上跑μC/OS-II的Nios II系統? (SOC) (Nios II) (μC/OS-II) (DE2-70)
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- (原創) 如何使用ModelSim-Altera對Nios II仿真? (SOC) (Nios II) (SOPC Builder) (ModelSim) (DE2)
- 跑"自己用SOPC Builder建立uC/OS-II范例"错误小结
- (原創) 如何從Nios II讀出CMOS放在SDRAM中的影像? (SOC) (SOPC Builder) (Nios II) (DE2-70) (TRDB-D5M) (TRDB-LTM)