Split transaction feature for Intel Pxa27x processor family

The system bus can be programmed to operate at a maximum frequency of 208 MHz to achieve the processor's highest level of performance.These system-bus clients are all high-speed devices that require fast access time.Rather than using a three-state approach,the bus is multiplexed and clients can request the bus without any limitations.

More peripherals are accessible through the peripheral bus,which itself is accessed through the DMA bridge.Regardless of the system-bus speed,the peripheral bus always runs at 26MHz to accommodate low-speed peripherals.

The interrupt controller is accessible through the low-speed peripheral bus.Because interrupt latency is critical for system performance,there is another interface exposed allowing the Intel XScale core to access interrupt controller via Coprocessor 6 quickly.With the exception of the ICCR and IPR,all interrupt controller registers are accessible through both the peripheral bus and Coprocessor 6 interfaces.

The split transaction feature should be enabled for two principal reasons:

1) to improve peripheral bus client access,

2) to avoid system bus client underruns.

1) Improving Peripheral Bus Client Access

With the system bus as high as 208MHz,the peripheral bus is always 26MHz;the throughput of the system bus is eight times that of the peripheral bus.With split transaction,transaction requests across the peripheral bus can be posted to the DMA bridge,which makes parallel accesses to the peripheral bus space feasible.

2) Avoid System Bus Client Underrun

When split transaction is disabled for read or write operation,the system bus is always owned by the XScale cor intil the read or write operation has completed,which causes underruns for system  bus clients such as LCD,camera,and others.Without split transaction enabled,high resolution camera images may be corrupted.

When Split Transaction is Disabled-Reads

A read transaction on the system bus is completed only after the DMA bridge receives the data from across the peripheral bus.There are no split responses,split completions,or retries in this mode.

See the following for a step-by-step description of a read transaction with split transaction disabled:

1: Core acquires the system bus

2: Core issues read command to the DMA bridge

3: Core stalls

4: Data is returned from the peripheral register to the DMA bridge,then to the core

5: Core activates and releases the system bus

When Split Transaction is Enabled-Reads

If the PIO transaction (PIO transaction is an I/O transaction read from a peripheral register or write to a peripheral register) is a read from a peripheral -address domain,the DMA split responds to the read instruction.The DMA bridge release the system bus,then uses micro-coded instructions to read data from the peripheral bus.Once the read completes across the peripheral bus,the DMA controller completes the split transaction by re-capturing the system bus and completing the PIO read transactions(read or writes)that occur while the current PIO read transaction is between the split response and the split completion will be retried.

See the following for a step-by-step description for read transactions with split transaction enabled:

1: Core acquires the system bus

2: Core issues a read command to the DMA bridge

3: Core releases system bus and stalls

4: Data is returned from peripheral register to the DMA bridge

5: DMA bridge acquires the system bus

6: DMA bridge returns the data back to core

7: Core activates and releases the system bus

System Bus impact

Following is the system-bus impact with the split transaction feature disabled/enabled.

Read:

 If disabled,the system bus is released only when data returns to the core(that is,the core and system bus are stalled).

 If enabled,the system bus is released once the read command reaches the DMA bridge(that is,the core is stalled but the systme bus is not stalled).

Ensure Earlier Write Takes Effect

As previously stated,when split transaction is enabled,the write is not safe-the core may continue execution assuming the previous write to the peripheral space took effect,when in fact it did not.

To ensure the earlier write to the peripheral-bus space takes effect,read back from the same address.For write-only registers,read from any location in the same peripheral address range.If the driver writes a few registers at one time,just one readback from the peripheral bus space is enough to ensure all the previous writes take effect.