Verilog 编程实验(3)-二位比较器的设计与实现

module comp2bit(a,b,a_eq_b,a_gt_b,a_lt_b);
input [1:0]a,b;
output a_eq_b,a_gt_b,a_lt_b;
assign a_eq_b = (a == b)? 1'b1: 1'b0;
assign a_gt_b = (a > b)? 1'b1: 1'b0;
assign a_lt_b = (a < b)? 1'b1: 1'b0;

endmodule

module comp2bitsTest2;

// Inputs
reg [1:0] a;
reg [1:0] b;

// Outputs
wire a_eq_b;
wire a_gt_b;
wire a_lt_b;

// Instantiate the Unit Under Test (UUT)
comp2bit uut (
.a(a),
.b(b),
.a_eq_b(a_eq_b),
.a_gt_b(a_gt_b),
.a_lt_b(a_lt_b)
);

initial begin
// Initialize Inputs
a = 0;
b = 0;

// Wait 100 ns for global reset to finish
#100;

// Add stimulus here
#200
a <= 2'b00;
b <= 2'b00;

#200
a <= 2'b00;
b <= 2'b01;

#200
a <= 2'b00;
b <= 2'b10;

#200
a <= 2'b00;
b <= 2'b11;

#200
a <= 2'b01;
b <= 2'b00;

#200
a <= 2'b01;
b <= 2'b01;

#200
a <= 2'b01;
b <= 2'b10;

#200
a <= 2'b01;
b <= 2'b11;

#200
a <= 2'b10;
b <= 2'b00;

#200
a <= 2'b10;
b <= 2'b01;

#200
a <= 2'b10;
b <= 2'b10;

#200
a <= 2'b10;
b <= 2'b11;

#200
a <= 2'b11;
b <= 2'b00;

#200
a <= 2'b11;
b <= 2'b01;

#200
a <= 2'b11;
b <= 2'b10;

#200
a <= 2'b11;
b <= 2'b11;
end

endmodule