数字电路设计之VGA显示条形图的verilog实现

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Engineer:       ChenYu
// Create Date:    18:38:12 11/05/2014 
// Design Name:    VGA
// Module Name:    vga_stripes_top 
// Project Name:   VGA
// Target Devices: ZedBoard
// Tool versions:  ISE 14.4
//////////////////////////////////////////////////////////////////////////////////
module vga_stripes_top(
		mclk,
		btn,
		hsync,
		vsync,
		red,
		green,
		blue
    );
	
	input wire       mclk;
	input wire       btn;
	output wire      hsync,vsync;
	output wire [2:0]green,red;
	output wire [1:0]blue;
	
	wire clk25,clr,vidon;
	wire [9:0] hc,vc;

	assign clr = btn;
	
	clkdiv U1(
		.mclk(mclk),
		.clr(clr),
		.clk25(clk25)
	);
	
	vga_640x480 V1(
		.clk(clk25),
		.clr(clr),
		.hsync(hsync),
		.vsync(vsync),
		.hc(hc),
		.vc(vc),
		.vidon(vidon)
	);
	
	vga_stripes V2(
		.vidon(vidon),
		.hc(hc),
		.vc(vc),
		.red(red),
		.green(green),
		.blue(blue)
	);

endmodule

module clkdiv(
	mclk,
	clr,
	clk25
    );

	input wire mclk;
	input wire clr;
	output wire clk25;
	//output wire clk48;
	
	reg  [24:0] q;
	//25位计数器
	always@(posedge mclk or posedge clr) begin
		if(clr)
			q <= 0;
		else 
			q <= q + 1;
	end
	
	assign clk25 = q[1];
	
endmodule

module vga_640x480(
	clk,
	clr,
	hsync,
	vsync,
	hc,
	vc,
	vidon
);

	input wire 			clk;
	input wire 			clr;
	output reg  		hsync;
	output reg          vsync;
	output reg   [9:0]  hc;
	output reg   [9:0]  vc;
	output reg          vidon;
	
	parameter hpixels = 10'b11001_00000; //行像素点=800
	parameter vlines = 10'b10000_01001;  //行数=521
	parameter hbp = 10'b001000_10000;//
	parameter hfp = 10'b11000_10000;
	parameter vbp =10'b00000_11111;
	parameter vfp = 10'b01111_11111;
	reg vsensable;  //enable for the vertical counter
	
	//行同步信号计数器·
	always@(posedge clk)  begin
		if(clr)
		 hc <= 0;
		else
		begin
			if(hc == hpixels - 1) begin
			hc <= 0;
			vsensable <= 1;
			//enable teh vertical counter to increase
			end
			else
			begin
			hc <= hc + 1;
			vsensable <= 0; //leave the vsenable off
			end		
		end
	end
	
	
	//产生hsync脉冲
	//当hc乾127的时候，行同步信号为低电幊	always@(*) begin
		if(hc < 96)
			hsync <= 0;
		else 
			hsync <= 1;
	end
	
	//场同步信号计数器
	always@(posedge clk) begin
		if(clr)
			vc <= 0;
		else begin
			if(vsensable == 1) begin
				if(vc == vlines - 1)
					vc <= 0;
				else 
					vc <= vc + 1;
			end
		end
	end
	
	//产生vsync脉冲
	//当hc书Ȗ聧ڄ时候，场同步脉冲为低电幊	
        always@(*) begin
		if( vc < 2) 
			vsync <= 0;
		else
			vsync <= 1;
	end
	
	always@(*) begin
		if((hc < hfp)&&(hc > hbp)&&(vc < vfp)&&(vc > vbp))
			vidon <= 1;
		else 
			vidon <= 0;
	end
	
endmodule

module vga_stripes(
		vidon,
		hc,
		vc,
		red,
		green,
		blue
    );

	input wire  		vidon;
	input wire  [9:0] hc,vc;
	output reg  [2:0] red,green;
	output reg  [1:0] blue;

	always@(*) begin
		if(vidon == 1) begin
			red <= {vc[4],vc[4],vc[4]};
			green <= {~vc[4],~vc[4],~vc[4]};
 		end
		else begin
			red   <= 0;
		   green <= 0;
		   blue  <= 0;
		end
	end

endmodule